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@@ -28,30 +28,19 @@
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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-#include <asm/smp_scu.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/timer-sp.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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-#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "core.h"
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#include "sysregs.h"
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void __iomem *sregs_base;
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-
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-#define HB_SCU_VIRT_BASE 0xfee00000
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-void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
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-
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-static struct map_desc scu_io_desc __initdata = {
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- .virtual = HB_SCU_VIRT_BASE,
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- .pfn = 0, /* run-time */
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- .length = SZ_4K,
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- .type = MT_DEVICE,
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-};
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+void __iomem *scu_base_addr;
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static void __init highbank_scu_map_io(void)
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{
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@@ -60,13 +49,11 @@ static void __init highbank_scu_map_io(void)
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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- scu_io_desc.pfn = __phys_to_pfn(base);
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- iotable_init(&scu_io_desc, 1);
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+ scu_base_addr = ioremap(base, SZ_4K);
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}
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static void __init highbank_map_io(void)
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{
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- highbank_scu_map_io();
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highbank_lluart_map_io();
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}
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@@ -99,6 +86,9 @@ static void __init highbank_init_irq(void)
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{
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of_irq_init(irq_match);
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+ if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
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+ highbank_scu_map_io();
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+
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#ifdef CONFIG_CACHE_L2X0
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/* Enable PL310 L2 Cache controller */
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highbank_smc1(0x102, 0x1);
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@@ -145,7 +135,6 @@ static struct sys_timer highbank_timer = {
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static void highbank_power_off(void)
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{
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hignbank_set_pwr_shutdown();
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- scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
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while (1)
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cpu_do_idle();
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