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@@ -1048,50 +1048,42 @@ pl08x_dma_tx_status(struct dma_chan *chan,
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/* PrimeCell DMA extension */
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struct burst_table {
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- int burstwords;
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+ u32 burstwords;
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u32 reg;
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};
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static const struct burst_table burst_sizes[] = {
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{
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.burstwords = 256,
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- .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
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+ .reg = PL080_BSIZE_256,
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},
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{
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.burstwords = 128,
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- .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
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+ .reg = PL080_BSIZE_128,
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},
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{
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.burstwords = 64,
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- .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
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+ .reg = PL080_BSIZE_64,
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},
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{
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.burstwords = 32,
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- .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
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+ .reg = PL080_BSIZE_32,
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},
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{
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.burstwords = 16,
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- .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
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+ .reg = PL080_BSIZE_16,
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},
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{
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.burstwords = 8,
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- .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
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+ .reg = PL080_BSIZE_8,
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},
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{
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.burstwords = 4,
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- .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
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+ .reg = PL080_BSIZE_4,
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},
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{
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- .burstwords = 1,
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- .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
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+ .burstwords = 0,
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+ .reg = PL080_BSIZE_1,
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},
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};
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@@ -1135,15 +1127,25 @@ static u32 pl08x_width(enum dma_slave_buswidth width)
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return ~0;
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}
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+static u32 pl08x_burst(u32 maxburst)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
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+ if (burst_sizes[i].burstwords <= maxburst)
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+ break;
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+
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+ return burst_sizes[i].reg;
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+}
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+
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static int dma_set_runtime_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
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struct pl08x_driver_data *pl08x = plchan->host;
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enum dma_slave_buswidth addr_width;
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- u32 width, maxburst;
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+ u32 width, burst, maxburst;
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u32 cctl = 0;
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- int i;
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if (!plchan->slave)
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return -EINVAL;
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@@ -1173,20 +1175,16 @@ static int dma_set_runtime_config(struct dma_chan *chan,
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cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
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/*
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- * Now decide on a maxburst:
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* If this channel will only request single transfers, set this
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* down to ONE element. Also select one element if no maxburst
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* is specified.
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*/
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- if (plchan->cd->single || maxburst == 0) {
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- cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
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- (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
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- } else {
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- for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
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- if (burst_sizes[i].burstwords <= maxburst)
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- break;
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- cctl |= burst_sizes[i].reg;
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- }
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+ if (plchan->cd->single)
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+ maxburst = 1;
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+
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+ burst = pl08x_burst(maxburst);
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+ cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
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+ cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
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if (plchan->runtime_direction == DMA_FROM_DEVICE) {
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plchan->src_addr = config->src_addr;
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