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@@ -596,7 +596,7 @@ static int __linearize(struct x86_emulate_ctxt *ctxt,
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if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
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goto bad;
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}
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- cpl = ctxt->ops->cpl(ctxt->vcpu);
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+ cpl = ctxt->ops->cpl(ctxt);
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rpl = ctxt->ops->get_segment_selector(ctxt, addr.seg) & 3;
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cpl = max(cpl, rpl);
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if (!(desc.type & 8)) {
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@@ -1248,7 +1248,7 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
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rpl = selector & 3;
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dpl = seg_desc.dpl;
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- cpl = ops->cpl(ctxt->vcpu);
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+ cpl = ops->cpl(ctxt);
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switch (seg) {
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case VCPU_SREG_SS:
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@@ -1407,7 +1407,7 @@ static int emulate_popf(struct x86_emulate_ctxt *ctxt,
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int rc;
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unsigned long val, change_mask;
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int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
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- int cpl = ops->cpl(ctxt->vcpu);
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+ int cpl = ops->cpl(ctxt);
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rc = emulate_pop(ctxt, ops, &val, len);
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if (rc != X86EMUL_CONTINUE)
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@@ -1852,7 +1852,7 @@ emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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setup_syscalls_segments(ctxt, ops, &cs, &ss);
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- ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
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+ ops->get_msr(ctxt, MSR_STAR, &msr_data);
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msr_data >>= 32;
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cs_sel = (u16)(msr_data & 0xfffc);
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ss_sel = (u16)(msr_data + 8);
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@@ -1871,17 +1871,17 @@ emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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#ifdef CONFIG_X86_64
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c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
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- ops->get_msr(ctxt->vcpu,
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+ ops->get_msr(ctxt,
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ctxt->mode == X86EMUL_MODE_PROT64 ?
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MSR_LSTAR : MSR_CSTAR, &msr_data);
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c->eip = msr_data;
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- ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
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+ ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
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ctxt->eflags &= ~(msr_data | EFLG_RF);
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#endif
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} else {
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/* legacy mode */
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- ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
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+ ops->get_msr(ctxt, MSR_STAR, &msr_data);
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c->eip = (u32)msr_data;
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ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
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@@ -1910,7 +1910,7 @@ emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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setup_syscalls_segments(ctxt, ops, &cs, &ss);
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- ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
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+ ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
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switch (ctxt->mode) {
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case X86EMUL_MODE_PROT32:
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if ((msr_data & 0xfffc) == 0x0)
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@@ -1938,10 +1938,10 @@ emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
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ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
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- ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
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+ ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
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c->eip = msr_data;
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- ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
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+ ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
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c->regs[VCPU_REGS_RSP] = msr_data;
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return X86EMUL_CONTINUE;
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@@ -1970,7 +1970,7 @@ emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
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cs.dpl = 3;
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ss.dpl = 3;
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- ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
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+ ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
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switch (usermode) {
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case X86EMUL_MODE_PROT32:
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cs_sel = (u16)(msr_data + 16);
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@@ -2010,7 +2010,7 @@ static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
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if (ctxt->mode == X86EMUL_MODE_VM86)
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return true;
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iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
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- return ops->cpl(ctxt->vcpu) > iopl;
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+ return ops->cpl(ctxt) > iopl;
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}
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static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
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@@ -2187,7 +2187,7 @@ static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
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{
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struct decode_cache *c = &ctxt->decode;
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- tss->cr3 = ops->get_cr(3, ctxt->vcpu);
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+ tss->cr3 = ops->get_cr(ctxt, 3);
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tss->eip = c->eip;
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tss->eflags = ctxt->eflags;
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tss->eax = c->regs[VCPU_REGS_RAX];
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@@ -2215,7 +2215,7 @@ static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
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struct decode_cache *c = &ctxt->decode;
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int ret;
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- if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
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+ if (ops->set_cr(ctxt, 3, tss->cr3))
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return emulate_gp(ctxt, 0);
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c->eip = tss->eip;
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ctxt->eflags = tss->eflags | 2;
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@@ -2338,7 +2338,7 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
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if (reason != TASK_SWITCH_IRET) {
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if ((tss_selector & 3) > next_tss_desc.dpl ||
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- ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
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+ ops->cpl(ctxt) > next_tss_desc.dpl)
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return emulate_gp(ctxt, 0);
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}
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@@ -2382,7 +2382,7 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
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&next_tss_desc);
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}
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- ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
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+ ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
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ops->set_cached_descriptor(ctxt, &next_tss_desc, 0, VCPU_SREG_TR);
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ops->set_segment_selector(ctxt, tss_selector, VCPU_SREG_TR);
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@@ -2542,7 +2542,7 @@ static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
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struct decode_cache *c = &ctxt->decode;
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u64 tsc = 0;
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- ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
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+ ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
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c->regs[VCPU_REGS_RAX] = (u32)tsc;
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c->regs[VCPU_REGS_RDX] = tsc >> 32;
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return X86EMUL_CONTINUE;
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@@ -2625,8 +2625,8 @@ static int check_cr_write(struct x86_emulate_ctxt *ctxt)
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((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
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return emulate_gp(ctxt, 0);
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- cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
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- ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
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+ cr4 = ctxt->ops->get_cr(ctxt, 4);
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+ ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
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if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
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!(cr4 & X86_CR4_PAE))
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@@ -2652,8 +2652,8 @@ static int check_cr_write(struct x86_emulate_ctxt *ctxt)
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case 4: {
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u64 cr4, efer;
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- cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
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- ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
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+ cr4 = ctxt->ops->get_cr(ctxt, 4);
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+ ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
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if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
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return emulate_gp(ctxt, 0);
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@@ -2669,7 +2669,7 @@ static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
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{
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unsigned long dr7;
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- ctxt->ops->get_dr(7, &dr7, ctxt->vcpu);
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+ ctxt->ops->get_dr(ctxt, 7, &dr7);
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/* Check if DR7.Global_Enable is set */
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return dr7 & (1 << 13);
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@@ -2684,7 +2684,7 @@ static int check_dr_read(struct x86_emulate_ctxt *ctxt)
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if (dr > 7)
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return emulate_ud(ctxt);
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- cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
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+ cr4 = ctxt->ops->get_cr(ctxt, 4);
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if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
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return emulate_ud(ctxt);
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@@ -2710,7 +2710,7 @@ static int check_svme(struct x86_emulate_ctxt *ctxt)
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{
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u64 efer;
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- ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
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+ ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
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if (!(efer & EFER_SVME))
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return emulate_ud(ctxt);
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@@ -2731,9 +2731,9 @@ static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
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static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
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{
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- u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
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+ u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
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- if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt->vcpu))
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+ if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
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return emulate_ud(ctxt);
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return X86EMUL_CONTINUE;
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@@ -2741,10 +2741,10 @@ static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
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static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
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{
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- u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
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+ u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
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u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX);
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- if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) ||
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+ if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
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(rcx > 3))
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return emulate_gp(ctxt, 0);
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@@ -3514,13 +3514,13 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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}
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if ((c->d & Sse)
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- && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM)
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- || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) {
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+ && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
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+ || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
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rc = emulate_ud(ctxt);
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goto done;
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}
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- if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) {
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+ if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
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rc = emulate_nm(ctxt);
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goto done;
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}
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@@ -3533,7 +3533,7 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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}
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/* Privileged instruction can be executed only in CPL=0 */
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- if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
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+ if ((c->d & Priv) && ops->cpl(ctxt)) {
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rc = emulate_gp(ctxt, 0);
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goto done;
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}
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@@ -4052,11 +4052,11 @@ twobyte_insn:
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break;
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case 4: /* smsw */
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c->dst.bytes = 2;
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- c->dst.val = ops->get_cr(0, ctxt->vcpu);
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+ c->dst.val = ops->get_cr(ctxt, 0);
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break;
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case 6: /* lmsw */
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- ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
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- (c->src.val & 0x0f), ctxt->vcpu);
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+ ops->set_cr(ctxt, 0, (ops->get_cr(ctxt, 0) & ~0x0eul) |
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+ (c->src.val & 0x0f));
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c->dst.type = OP_NONE;
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break;
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case 5: /* not defined */
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@@ -4084,13 +4084,13 @@ twobyte_insn:
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case 0x18: /* Grp16 (prefetch/nop) */
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break;
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case 0x20: /* mov cr, reg */
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- c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
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+ c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
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break;
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case 0x21: /* mov from dr to reg */
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- ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
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+ ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
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break;
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case 0x22: /* mov reg, cr */
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- if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
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+ if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
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emulate_gp(ctxt, 0);
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rc = X86EMUL_PROPAGATE_FAULT;
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goto done;
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@@ -4098,9 +4098,9 @@ twobyte_insn:
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c->dst.type = OP_NONE;
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break;
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case 0x23: /* mov from reg to dr */
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- if (ops->set_dr(c->modrm_reg, c->src.val &
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+ if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
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((ctxt->mode == X86EMUL_MODE_PROT64) ?
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- ~0ULL : ~0U), ctxt->vcpu) < 0) {
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+ ~0ULL : ~0U)) < 0) {
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/* #UD condition is already handled by the code above */
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emulate_gp(ctxt, 0);
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rc = X86EMUL_PROPAGATE_FAULT;
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@@ -4113,7 +4113,7 @@ twobyte_insn:
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/* wrmsr */
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msr_data = (u32)c->regs[VCPU_REGS_RAX]
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| ((u64)c->regs[VCPU_REGS_RDX] << 32);
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- if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
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+ if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
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emulate_gp(ctxt, 0);
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rc = X86EMUL_PROPAGATE_FAULT;
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goto done;
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@@ -4122,7 +4122,7 @@ twobyte_insn:
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break;
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case 0x32:
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/* rdmsr */
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- if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
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+ if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
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emulate_gp(ctxt, 0);
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rc = X86EMUL_PROPAGATE_FAULT;
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goto done;
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