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@@ -533,13 +533,14 @@ static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
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/* Form out message */
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snprintf(msg, sizeof(msg),
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- "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d CAS=%d "
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- "FATAL Err=0x%x (%s))",
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- branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
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- allErrors, specific);
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+ "Bank=%d RAS=%d CAS=%d FATAL Err=0x%x (%s)",
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+ bank, ras, cas, allErrors, specific);
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/* Call the helper to output message */
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- edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
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+ edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 0, 0, 0,
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+ branch >> 1, -1, rank,
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+ rdwr ? "Write error" : "Read error",
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+ msg, NULL);
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}
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/*
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@@ -633,13 +634,14 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
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/* Form out message */
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snprintf(msg, sizeof(msg),
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- "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
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- "CAS=%d, UE Err=0x%x (%s))",
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- branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
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- ue_errors, specific);
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+ "Rank=%d Bank=%d RAS=%d CAS=%d, UE Err=0x%x (%s)",
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+ rank, bank, ras, cas, ue_errors, specific);
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/* Call the helper to output message */
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- edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
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+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
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+ channel >> 1, -1, rank,
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+ rdwr ? "Write error" : "Read error",
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+ msg, NULL);
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}
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/* Check correctable errors */
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@@ -685,13 +687,16 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
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/* Form out message */
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snprintf(msg, sizeof(msg),
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- "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
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+ "Rank=%d Bank=%d RDWR=%s RAS=%d "
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"CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
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rdwr ? "Write" : "Read", ras, cas, ce_errors,
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specific);
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/* Call the helper to output message */
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- edac_mc_handle_fbd_ce(mci, rank, channel, msg);
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+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
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+ channel >> 1, channel % 2, rank,
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+ rdwr ? "Write error" : "Read error",
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+ msg, NULL);
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}
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if (!misc_messages)
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@@ -731,11 +736,12 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
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/* Form out message */
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snprintf(msg, sizeof(msg),
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- "(Branch=%d Err=%#x (%s))", branch >> 1,
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- misc_errors, specific);
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+ "Err=%#x (%s)", misc_errors, specific);
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/* Call the helper to output message */
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- edac_mc_handle_fbd_ce(mci, 0, 0, msg);
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+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
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+ branch >> 1, -1, -1,
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+ "Misc error", msg, NULL);
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}
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}
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@@ -1251,6 +1257,10 @@ static int i5000_init_csrows(struct mem_ctl_info *mci)
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empty = 1; /* Assume NO memory */
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+ /*
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+ * TODO: it would be better to not use csrow here, filling
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+ * directly the dimm_info structs, based on branch, channel, dim number
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+ */
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for (csrow = 0; csrow < max_csrows; csrow++) {
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p_csrow = &mci->csrows[csrow];
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@@ -1312,7 +1322,7 @@ static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
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}
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/*
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- * i5000_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
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+ * i5000_get_dimm_and_channel_counts(pdev, &nr_csrows, &num_channels)
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*
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* ask the device how many channels are present and how many CSROWS
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* as well
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@@ -1343,10 +1353,10 @@ static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
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static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
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{
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struct mem_ctl_info *mci;
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+ struct edac_mc_layer layers[3];
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struct i5000_pvt *pvt;
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int num_channels;
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int num_dimms_per_channel;
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- int num_csrows;
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debugf0("MC: %s: %s(), pdev bus %u dev=0x%x fn=0x%x\n",
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__FILE__, __func__,
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@@ -1372,13 +1382,21 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
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*/
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i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
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&num_channels);
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- num_csrows = num_dimms_per_channel * 2;
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- debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
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- __func__, num_channels, num_dimms_per_channel, num_csrows);
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+ debugf0("MC: %s(): Number of Branches=2 Channels= %d DIMMS= %d\n",
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+ __func__, num_channels, num_dimms_per_channel);
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/* allocate a new MC control structure */
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- mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
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+ layers[0].type = EDAC_MC_LAYER_BRANCH;
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+ layers[0].size = 2;
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+ layers[0].is_virt_csrow = true;
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+ layers[1].type = EDAC_MC_LAYER_CHANNEL;
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+ layers[1].size = num_channels;
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+ layers[1].is_virt_csrow = false;
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+ layers[2].type = EDAC_MC_LAYER_SLOT;
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+ layers[2].size = num_dimms_per_channel;
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+ layers[2].is_virt_csrow = true;
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+ mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
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if (mci == NULL)
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return -ENOMEM;
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