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@@ -23,6 +23,7 @@
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#define PCI_DEVICE_ID_INTEL_3200_HB 0x29f0
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+#define I3200_DIMMS 4
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#define I3200_RANKS 8
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#define I3200_RANKS_PER_CHANNEL 4
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#define I3200_CHANNELS 2
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@@ -217,21 +218,25 @@ static void i3200_process_error_info(struct mem_ctl_info *mci,
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return;
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if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
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- edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
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+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
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+ -1, -1, -1, "UE overwrote CE", "", NULL);
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info->errsts = info->errsts2;
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}
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for (channel = 0; channel < nr_channels; channel++) {
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log = info->eccerrlog[channel];
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if (log & I3200_ECCERRLOG_UE) {
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- edac_mc_handle_ue(mci, 0, 0,
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- eccerrlog_row(channel, log),
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- "i3200 UE");
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+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
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+ 0, 0, 0,
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+ eccerrlog_row(channel, log),
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+ -1, -1,
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+ "i3000 UE", "", NULL);
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} else if (log & I3200_ECCERRLOG_CE) {
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- edac_mc_handle_ce(mci, 0, 0,
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- eccerrlog_syndrome(log),
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- eccerrlog_row(channel, log), 0,
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- "i3200 CE");
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+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
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+ 0, 0, eccerrlog_syndrome(log),
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+ eccerrlog_row(channel, log),
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+ -1, -1,
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+ "i3000 UE", "", NULL);
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}
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}
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}
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@@ -321,6 +326,7 @@ static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
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int rc;
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int i, j;
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struct mem_ctl_info *mci = NULL;
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+ struct edac_mc_layer layers[2];
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u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
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bool stacked;
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void __iomem *window;
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@@ -335,8 +341,14 @@ static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
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i3200_get_drbs(window, drbs);
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nr_channels = how_many_channels(pdev);
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- mci = edac_mc_alloc(sizeof(struct i3200_priv), I3200_RANKS,
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- nr_channels, 0);
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+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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+ layers[0].size = I3200_DIMMS;
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+ layers[0].is_virt_csrow = true;
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+ layers[1].type = EDAC_MC_LAYER_CHANNEL;
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+ layers[1].size = nr_channels;
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+ layers[1].is_virt_csrow = false;
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+ mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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+ sizeof(struct i3200_priv));
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if (!mci)
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return -ENOMEM;
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