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@@ -119,18 +119,19 @@ enum {
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PIIX_80C_SEC = (1 << 7) | (1 << 6),
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/* controller IDs */
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- piix_pata_33 = 0, /* PIIX4 at 33Mhz */
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- ich_pata_33 = 1, /* ICH up to UDMA 33 only */
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- ich_pata_66 = 2, /* ICH up to 66 Mhz */
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- ich_pata_100 = 3, /* ICH up to UDMA 100 */
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- ich5_sata = 5,
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- ich6_sata = 6,
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- ich6_sata_ahci = 7,
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- ich6m_sata_ahci = 8,
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- ich8_sata_ahci = 9,
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- piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
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- tolapai_sata_ahci = 11,
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- ich9_2port_sata = 12,
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+ piix_pata_mwdma = 0, /* PIIX3 MWDMA only */
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+ piix_pata_33, /* PIIX4 at 33Mhz */
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+ ich_pata_33, /* ICH up to UDMA 33 only */
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+ ich_pata_66, /* ICH up to 66 Mhz */
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+ ich_pata_100, /* ICH up to UDMA 100 */
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+ ich5_sata,
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+ ich6_sata,
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+ ich6_sata_ahci,
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+ ich6m_sata_ahci,
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+ ich8_sata_ahci,
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+ ich8_2port_sata,
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+ ich8m_apple_sata_ahci, /* locks up on second port enable */
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+ tolapai_sata_ahci,
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/* constants for mapping table */
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P0 = 0, /* port 0 */
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@@ -239,19 +240,21 @@ static const struct pci_device_id piix_pci_tbl[] = {
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/* SATA Controller 1 IDE (ICH8) */
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{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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/* SATA Controller 2 IDE (ICH8) */
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- { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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+ { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* Mobile SATA Controller IDE (ICH8M) */
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{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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+ /* Mobile SATA Controller IDE (ICH8M), Apple */
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+ { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
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/* SATA Controller IDE (ICH9) */
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{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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/* SATA Controller IDE (ICH9) */
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- { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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+ { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* SATA Controller IDE (ICH9) */
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- { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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+ { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* SATA Controller IDE (ICH9M) */
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- { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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+ { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* SATA Controller IDE (ICH9M) */
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- { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
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+ { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* SATA Controller IDE (ICH9M) */
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{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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/* SATA Controller IDE (Tolapai) */
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@@ -427,7 +430,7 @@ static const struct piix_map_db ich6m_map_db = {
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static const struct piix_map_db ich8_map_db = {
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.mask = 0x3,
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- .port_enable = 0x3,
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+ .port_enable = 0xf,
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.map = {
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/* PM PS SM SS MAP */
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{ P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
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@@ -437,7 +440,7 @@ static const struct piix_map_db ich8_map_db = {
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},
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};
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-static const struct piix_map_db tolapai_map_db = {
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+static const struct piix_map_db ich8_2port_map_db = {
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.mask = 0x3,
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.port_enable = 0x3,
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.map = {
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@@ -449,7 +452,19 @@ static const struct piix_map_db tolapai_map_db = {
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},
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};
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-static const struct piix_map_db ich9_2port_map_db = {
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+static const struct piix_map_db ich8m_apple_map_db = {
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+ .mask = 0x3,
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+ .port_enable = 0x1,
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+ .map = {
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+ /* PM PS SM SS MAP */
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+ { P0, NA, NA, NA }, /* 00b */
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+ { RV, RV, RV, RV },
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+ { P0, P2, IDE, IDE }, /* 10b */
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+ { RV, RV, RV, RV },
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+ },
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+};
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+
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+static const struct piix_map_db tolapai_map_db = {
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.mask = 0x3,
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.port_enable = 0x3,
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.map = {
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@@ -467,11 +482,21 @@ static const struct piix_map_db *piix_map_db_table[] = {
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[ich6_sata_ahci] = &ich6_map_db,
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[ich6m_sata_ahci] = &ich6m_map_db,
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[ich8_sata_ahci] = &ich8_map_db,
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+ [ich8_2port_sata] = &ich8_2port_map_db,
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+ [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
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[tolapai_sata_ahci] = &tolapai_map_db,
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- [ich9_2port_sata] = &ich9_2port_map_db,
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};
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static struct ata_port_info piix_port_info[] = {
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+ [piix_pata_mwdma] = /* PIIX3 MWDMA only */
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+ {
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+ .sht = &piix_sht,
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+ .flags = PIIX_PATA_FLAGS,
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+ .pio_mask = 0x1f, /* pio0-4 */
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+ .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
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+ .port_ops = &piix_pata_ops,
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+ },
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+
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[piix_pata_33] = /* PIIX4 at 33MHz */
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{
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.sht = &piix_sht,
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@@ -565,13 +590,15 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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},
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- [piix_pata_mwdma] = /* PIIX3 MWDMA only */
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+ [ich8_2port_sata] =
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{
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.sht = &piix_sht,
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- .flags = PIIX_PATA_FLAGS,
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+ .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
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+ PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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- .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
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- .port_ops = &piix_pata_ops,
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+ .mwdma_mask = 0x07, /* mwdma0-2 */
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+ .udma_mask = ATA_UDMA6,
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+ .port_ops = &piix_sata_ops,
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},
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[tolapai_sata_ahci] =
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@@ -585,7 +612,7 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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},
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- [ich9_2port_sata] =
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+ [ich8m_apple_sata_ahci] =
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{
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.sht = &piix_sht,
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.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
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@@ -595,6 +622,7 @@ static struct ata_port_info piix_port_info[] = {
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.udma_mask = ATA_UDMA6,
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.port_ops = &piix_sata_ops,
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},
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+
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};
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static struct pci_bits piix_enable_bits[] = {
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@@ -973,6 +1001,13 @@ static int piix_broken_suspend(void)
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DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
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},
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},
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+ {
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+ .ident = "SATELLITE U205",
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+ .matches = {
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+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
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+ DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
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+ },
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+ },
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{
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.ident = "Portege M500",
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.matches = {
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@@ -1086,12 +1121,12 @@ static int piix_disable_ahci(struct pci_dev *pdev)
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if (!mmio)
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return -ENOMEM;
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- tmp = readl(mmio + AHCI_GLOBAL_CTL);
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+ tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
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if (tmp & AHCI_ENABLE) {
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tmp &= ~AHCI_ENABLE;
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- writel(tmp, mmio + AHCI_GLOBAL_CTL);
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+ iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
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- tmp = readl(mmio + AHCI_GLOBAL_CTL);
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+ tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
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if (tmp & AHCI_ENABLE)
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rc = -EIO;
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}
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