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@@ -173,7 +173,7 @@
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/* RPS clock parameters. */
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#define RPSCLK_SCALAR 8 /* This is apparent ratio of PCI/RPS clks (undocumented!!). */
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-#define RPSCLK_PER_US ( 33 / RPSCLK_SCALAR ) /* Number of RPS clocks in one microsecond. */
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+#define RPSCLK_PER_US (33 / RPSCLK_SCALAR) /* Number of RPS clocks in one microsecond. */
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/* Event counter source addresses. */
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#define SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */
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@@ -377,14 +377,14 @@
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#if PLATFORM == INTEL /* Base ACON1 config: always run A1 based
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* on TSL1. */
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-#define ACON1_BASE ( WS_MODES | A1_RUN )
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+#define ACON1_BASE (WS_MODES | A1_RUN)
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#elif PLATFORM == MOTOROLA
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-#define ACON1_BASE ( WS_MODES | A1_RUN | A1_SWAP | A2_SWAP )
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+#define ACON1_BASE (WS_MODES | A1_RUN | A1_SWAP | A2_SWAP)
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#endif
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#define ACON1_ADCSTART ACON1_BASE /* Start ADC: run A1
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* based on TSL1. */
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-#define ACON1_DACSTART ( ACON1_BASE | A2_RUN )
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+#define ACON1_DACSTART (ACON1_BASE | A2_RUN)
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/* Start transmit to DAC: run A2 based on TSL2. */
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#define ACON1_DACSTOP ACON1_BASE /* Halt A2. */
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@@ -398,7 +398,7 @@
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#define ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 */
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/* active-low bits. */
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-#define ACON2_INIT ( ACON2_XORMASK ^ ( A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | INVERT_BCLK2 | BCLK2_OE ) )
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+#define ACON2_INIT (ACON2_XORMASK ^ (A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | INVERT_BCLK2 | BCLK2_OE))
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/* Bit masks for timeslot records. */
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#define WS1 0x40000000 /* WS output to assert. */
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@@ -452,7 +452,7 @@
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/* I2C manifest constants. */
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/* Max retries to wait for EEPROM write. */
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-#define I2C_RETRIES ( I2C_WRTIME * I2C_BITRATE / 9.0 )
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+#define I2C_RETRIES (I2C_WRTIME * I2C_BITRATE / 9.0)
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#define I2C_ERR 0x0002 /* I2C control/status */
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/* flag ERROR. */
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#define I2C_BUSY 0x0001 /* I2C control/status */
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@@ -464,15 +464,15 @@
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#define I2C_ATTRNOP 0x0 /* I2C attribute NOP. */
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/* I2C read command | EEPROM address. */
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-#define I2CR ( devpriv->I2CAdrs | 1 )
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+#define I2CR (devpriv->I2CAdrs | 1)
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/* I2C write command | EEPROM address. */
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-#define I2CW ( devpriv->I2CAdrs )
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+#define I2CW (devpriv->I2CAdrs)
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/* Code macros used for constructing I2C command bytes. */
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-#define I2C_B2(ATTR, VAL) ( ( (ATTR) << 6 ) | ( (VAL) << 24 ) )
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-#define I2C_B1(ATTR, VAL) ( ( (ATTR) << 4 ) | ( (VAL) << 16 ) )
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-#define I2C_B0(ATTR, VAL) ( ( (ATTR) << 2 ) | ( (VAL) << 8 ) )
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+#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
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+#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
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+#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
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/* oldest */
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#define P_DEBICFGq 0x007C /* DEBI configuration. */
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@@ -490,16 +490,16 @@
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#define DEBI_PAGE_DISABLEQ 0x00000000 /* paging disable */
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/* DEBI command constants. */
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-#define DEBI_CMD_SIZE16 ( 2 << 17 ) /* Transfer size is */
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+#define DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is */
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/* always 2 bytes. */
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#define DEBI_CMD_READ 0x00010000 /* Read operation. */
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#define DEBI_CMD_WRITE 0x00000000 /* Write operation. */
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/* Read immediate 2 bytes. */
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-#define DEBI_CMD_RDWORD ( DEBI_CMD_READ | DEBI_CMD_SIZE16 )
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+#define DEBI_CMD_RDWORD (DEBI_CMD_READ | DEBI_CMD_SIZE16)
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/* Write immediate 2 bytes. */
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-#define DEBI_CMD_WRWORD ( DEBI_CMD_WRITE | DEBI_CMD_SIZE16 )
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+#define DEBI_CMD_WRWORD (DEBI_CMD_WRITE | DEBI_CMD_SIZE16)
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/* DEBI configuration constants. */
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#define DEBI_CFG_XIRQ_EN 0x80000000 /* enab external */
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@@ -681,29 +681,29 @@
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/* Bit field masks for CRA and CRB. */
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-#define CRAMSK_INDXSRC_B ( (uint16_t)( 3 << CRABIT_INDXSRC_B) )
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-#define CRAMSK_CLKSRC_B ( (uint16_t)( 3 << CRABIT_CLKSRC_B) )
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-#define CRAMSK_INDXPOL_A ( (uint16_t)( 1 << CRABIT_INDXPOL_A) )
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-#define CRAMSK_LOADSRC_A ( (uint16_t)( 3 << CRABIT_LOADSRC_A) )
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-#define CRAMSK_CLKMULT_A ( (uint16_t)( 3 << CRABIT_CLKMULT_A) )
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-#define CRAMSK_INTSRC_A ( (uint16_t)( 3 << CRABIT_INTSRC_A) )
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-#define CRAMSK_CLKPOL_A ( (uint16_t)( 3 << CRABIT_CLKPOL_A) )
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-#define CRAMSK_INDXSRC_A ( (uint16_t)( 3 << CRABIT_INDXSRC_A) )
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-#define CRAMSK_CLKSRC_A ( (uint16_t)( 3 << CRABIT_CLKSRC_A) )
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-
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-#define CRBMSK_INTRESETCMD ( (uint16_t)( 1 << CRBBIT_INTRESETCMD) )
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-#define CRBMSK_INTRESET_B ( (uint16_t)( 1 << CRBBIT_INTRESET_B) )
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-#define CRBMSK_INTRESET_A ( (uint16_t)( 1 << CRBBIT_INTRESET_A) )
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-#define CRBMSK_CLKENAB_A ( (uint16_t)( 1 << CRBBIT_CLKENAB_A) )
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-#define CRBMSK_INTSRC_B ( (uint16_t)( 3 << CRBBIT_INTSRC_B) )
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-#define CRBMSK_LATCHSRC ( (uint16_t)( 3 << CRBBIT_LATCHSRC) )
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-#define CRBMSK_LOADSRC_B ( (uint16_t)( 3 << CRBBIT_LOADSRC_B) )
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-#define CRBMSK_CLKMULT_B ( (uint16_t)( 3 << CRBBIT_CLKMULT_B) )
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-#define CRBMSK_CLKENAB_B ( (uint16_t)( 1 << CRBBIT_CLKENAB_B) )
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-#define CRBMSK_INDXPOL_B ( (uint16_t)( 1 << CRBBIT_INDXPOL_B) )
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-#define CRBMSK_CLKPOL_B ( (uint16_t)( 1 << CRBBIT_CLKPOL_B) )
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-
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-#define CRBMSK_INTCTRL ( CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B ) /* Interrupt reset control bits. */
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+#define CRAMSK_INDXSRC_B ((uint16_t)(3 << CRABIT_INDXSRC_B))
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+#define CRAMSK_CLKSRC_B ((uint16_t)(3 << CRABIT_CLKSRC_B))
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+#define CRAMSK_INDXPOL_A ((uint16_t)(1 << CRABIT_INDXPOL_A))
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+#define CRAMSK_LOADSRC_A ((uint16_t)(3 << CRABIT_LOADSRC_A))
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+#define CRAMSK_CLKMULT_A ((uint16_t)(3 << CRABIT_CLKMULT_A))
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+#define CRAMSK_INTSRC_A ((uint16_t)(3 << CRABIT_INTSRC_A))
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+#define CRAMSK_CLKPOL_A ((uint16_t)(3 << CRABIT_CLKPOL_A))
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+#define CRAMSK_INDXSRC_A ((uint16_t)(3 << CRABIT_INDXSRC_A))
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+#define CRAMSK_CLKSRC_A ((uint16_t)(3 << CRABIT_CLKSRC_A))
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+
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+#define CRBMSK_INTRESETCMD ((uint16_t)(1 << CRBBIT_INTRESETCMD))
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+#define CRBMSK_INTRESET_B ((uint16_t)(1 << CRBBIT_INTRESET_B))
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+#define CRBMSK_INTRESET_A ((uint16_t)(1 << CRBBIT_INTRESET_A))
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+#define CRBMSK_CLKENAB_A ((uint16_t)(1 << CRBBIT_CLKENAB_A))
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+#define CRBMSK_INTSRC_B ((uint16_t)(3 << CRBBIT_INTSRC_B))
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+#define CRBMSK_LATCHSRC ((uint16_t)(3 << CRBBIT_LATCHSRC))
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+#define CRBMSK_LOADSRC_B ((uint16_t)(3 << CRBBIT_LOADSRC_B))
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+#define CRBMSK_CLKMULT_B ((uint16_t)(3 << CRBBIT_CLKMULT_B))
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+#define CRBMSK_CLKENAB_B ((uint16_t)(1 << CRBBIT_CLKENAB_B))
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+#define CRBMSK_INDXPOL_B ((uint16_t)(1 << CRBBIT_INDXPOL_B))
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+#define CRBMSK_CLKPOL_B ((uint16_t)(1 << CRBBIT_CLKPOL_B))
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+
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+#define CRBMSK_INTCTRL (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B) /* Interrupt reset control bits. */
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/* Bit field positions for standardized SETUP structure. */
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@@ -719,15 +719,15 @@
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/* Bit field masks for standardized SETUP structure. */
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-#define STDMSK_INTSRC ( (uint16_t)( 3 << STDBIT_INTSRC ) )
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-#define STDMSK_LATCHSRC ( (uint16_t)( 3 << STDBIT_LATCHSRC ) )
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-#define STDMSK_LOADSRC ( (uint16_t)( 3 << STDBIT_LOADSRC ) )
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-#define STDMSK_INDXSRC ( (uint16_t)( 1 << STDBIT_INDXSRC ) )
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-#define STDMSK_INDXPOL ( (uint16_t)( 1 << STDBIT_INDXPOL ) )
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-#define STDMSK_CLKSRC ( (uint16_t)( 3 << STDBIT_CLKSRC ) )
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-#define STDMSK_CLKPOL ( (uint16_t)( 1 << STDBIT_CLKPOL ) )
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-#define STDMSK_CLKMULT ( (uint16_t)( 3 << STDBIT_CLKMULT ) )
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-#define STDMSK_CLKENAB ( (uint16_t)( 1 << STDBIT_CLKENAB ) )
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+#define STDMSK_INTSRC ((uint16_t)(3 << STDBIT_INTSRC))
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+#define STDMSK_LATCHSRC ((uint16_t)(3 << STDBIT_LATCHSRC))
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+#define STDMSK_LOADSRC ((uint16_t)(3 << STDBIT_LOADSRC))
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+#define STDMSK_INDXSRC ((uint16_t)(1 << STDBIT_INDXSRC))
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+#define STDMSK_INDXPOL ((uint16_t)(1 << STDBIT_INDXPOL))
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+#define STDMSK_CLKSRC ((uint16_t)(3 << STDBIT_CLKSRC))
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+#define STDMSK_CLKPOL ((uint16_t)(1 << STDBIT_CLKPOL))
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+#define STDMSK_CLKMULT ((uint16_t)(3 << STDBIT_CLKMULT))
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+#define STDMSK_CLKENAB ((uint16_t)(1 << STDBIT_CLKENAB))
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/* typedef struct indexCounter */
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