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@@ -33,6 +33,10 @@
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#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
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#define MV64XXX_I2C_REG_SOFT_RESET 0x1c
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+#define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
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+#define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
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+#define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
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+
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#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
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#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
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#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
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@@ -133,7 +137,7 @@ mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
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drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
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drv_data->addr2 = (u32)msg->addr & 0xff;
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} else {
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- drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
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+ drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
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drv_data->addr2 = 0;
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}
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}
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@@ -151,7 +155,7 @@ static void
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mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
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{
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writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
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- writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
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+ writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
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drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
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writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
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writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
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