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@@ -160,6 +160,38 @@ extern int radeon_aspm;
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#define RADEON_CG_BLOCK_VCE (1 << 4)
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#define RADEON_CG_BLOCK_HDP (1 << 5)
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+/* CG flags */
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+#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
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+#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
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+#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
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+#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
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+#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
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+#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
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+#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
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+#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
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+#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
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+#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
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+#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
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+#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
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+#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
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+#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
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+#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
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+#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
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+#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
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+
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+/* PG flags */
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+#define RADEON_PG_SUPPORT_GFX_CG (1 << 0)
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+#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
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+#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
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+#define RADEON_PG_SUPPORT_UVD (1 << 3)
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+#define RADEON_PG_SUPPORT_VCE (1 << 4)
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+#define RADEON_PG_SUPPORT_CP (1 << 5)
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+#define RADEON_PG_SUPPORT_GDS (1 << 6)
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+#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
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+#define RADEON_PG_SUPPORT_SDMA (1 << 8)
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+#define RADEON_PG_SUPPORT_ACP (1 << 9)
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+#define RADEON_PG_SUPPORT_SAMU (1 << 10)
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+
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/* max cursor sizes (in pixels) */
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#define CURSOR_WIDTH 64
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#define CURSOR_HEIGHT 64
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@@ -2156,6 +2188,9 @@ struct radeon_device {
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struct radeon_atcs atcs;
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/* srbm instance registers */
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struct mutex srbm_mutex;
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+ /* clock, powergating flags */
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+ u32 cg_flags;
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+ u32 pg_flags;
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};
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int radeon_device_init(struct radeon_device *rdev,
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