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@@ -283,6 +283,45 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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}
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}
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+static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
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+{
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+ struct radeon_device *rdev = encoder->dev->dev_private;
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+ struct drm_connector *connector;
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+ struct radeon_connector *radeon_connector = NULL;
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+ u32 tmp;
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+ u8 *sadb;
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+ int sad_count;
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+
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+ list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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+ if (connector->encoder == encoder)
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+ radeon_connector = to_radeon_connector(connector);
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+ }
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+
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+ if (!radeon_connector) {
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+ DRM_ERROR("Couldn't find encoder's connector\n");
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+ return;
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+ }
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+
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+ sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
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+ if (sad_count < 0) {
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+ DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
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+ return;
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+ }
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+
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+ /* program the speaker allocation */
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+ tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
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+ tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
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+ /* set HDMI mode */
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+ tmp |= HDMI_CONNECTION;
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+ if (sad_count)
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+ tmp |= SPEAKER_ALLOCATION(sadb[0]);
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+ else
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+ tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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+ WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
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+
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+ kfree(sadb);
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+}
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+
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/*
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* update the info frames with the data from the current display mode
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*/
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@@ -327,6 +366,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
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}
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+ if (ASIC_IS_DCE32(rdev))
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+ dce3_2_afmt_write_speaker_allocation(encoder);
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+
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WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
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HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
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HDMI0_ACR_SOURCE); /* select SW CTS value */
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