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@@ -58,6 +58,45 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc
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WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
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}
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+static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
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+{
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+ struct radeon_device *rdev = encoder->dev->dev_private;
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+ struct drm_connector *connector;
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+ struct radeon_connector *radeon_connector = NULL;
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+ u32 tmp;
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+ u8 *sadb;
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+ int sad_count;
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+
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+ list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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+ if (connector->encoder == encoder)
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+ radeon_connector = to_radeon_connector(connector);
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+ }
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+
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+ if (!radeon_connector) {
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+ DRM_ERROR("Couldn't find encoder's connector\n");
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+ return;
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+ }
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+
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+ sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
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+ if (sad_count < 0) {
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+ DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
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+ return;
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+ }
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+
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+ /* program the speaker allocation */
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+ tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
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+ tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
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+ /* set HDMI mode */
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+ tmp |= HDMI_CONNECTION;
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+ if (sad_count)
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+ tmp |= SPEAKER_ALLOCATION(sadb[0]);
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+ else
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+ tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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+ WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
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+
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+ kfree(sadb);
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+}
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+
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static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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@@ -271,7 +310,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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if (ASIC_IS_DCE6(rdev)) {
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dce6_afmt_write_speaker_allocation(encoder);
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} else {
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- /* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
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+ dce4_afmt_write_speaker_allocation(encoder);
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}
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WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
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