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@@ -179,10 +179,11 @@ static int r82600_process_error_info(struct mem_ctl_info *mci,
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error_found = 1;
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if (handle_errors)
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- edac_mc_handle_ce(mci, page, 0, /* not avail */
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- syndrome,
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- edac_mc_find_csrow_by_page(mci, page),
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- 0, mci->ctl_name);
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+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
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+ page, 0, syndrome,
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+ edac_mc_find_csrow_by_page(mci, page),
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+ 0, -1,
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+ mci->ctl_name, "", NULL);
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}
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if (info->eapr & BIT(1)) { /* UE? */
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@@ -190,9 +191,11 @@ static int r82600_process_error_info(struct mem_ctl_info *mci,
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if (handle_errors)
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/* 82600 doesn't give enough info */
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- edac_mc_handle_ue(mci, page, 0,
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- edac_mc_find_csrow_by_page(mci, page),
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- mci->ctl_name);
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+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
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+ page, 0, 0,
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+ edac_mc_find_csrow_by_page(mci, page),
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+ 0, -1,
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+ mci->ctl_name, "", NULL);
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}
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return error_found;
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@@ -267,6 +270,7 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
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static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
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{
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struct mem_ctl_info *mci;
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+ struct edac_mc_layer layers[2];
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u8 dramcr;
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u32 eapr;
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u32 scrub_disabled;
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@@ -281,8 +285,13 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
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debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
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sdram_refresh_rate);
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debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
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- mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS, 0);
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-
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+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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+ layers[0].size = R82600_NR_CSROWS;
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+ layers[0].is_virt_csrow = true;
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+ layers[1].type = EDAC_MC_LAYER_CHANNEL;
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+ layers[1].size = R82600_NR_CHANS;
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+ layers[1].is_virt_csrow = false;
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+ mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
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if (mci == NULL)
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return -ENOMEM;
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