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@@ -243,8 +243,11 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
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/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
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_omap3_noncore_dpll_bypass(clk);
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- /* Set jitter correction */
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- if (!cpu_is_omap44xx()) {
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+ /*
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+ * Set jitter correction. No jitter correction for OMAP4 and 3630
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+ * since freqsel field is no longer present
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+ */
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+ if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
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v = __raw_readl(dd->control_reg);
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v &= ~dd->freqsel_mask;
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v |= freqsel << __ffs(dd->freqsel_mask);
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@@ -387,8 +390,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
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if (dd->last_rounded_rate == 0)
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return -EINVAL;
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- /* No freqsel on OMAP4 */
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- if (!cpu_is_omap44xx()) {
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+ /* No freqsel on OMAP4 and OMAP3630 */
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+ if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
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freqsel = _omap3_dpll_compute_freqsel(clk,
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dd->last_rounded_n);
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if (!freqsel)
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