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@@ -1206,7 +1206,7 @@ static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
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static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
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{
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- if (sp->role.glevels != vcpu->arch.mmu.root_level) {
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+ if (sp->role.cr4_pae != !!is_pae(vcpu)) {
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kvm_mmu_zap_page(vcpu->kvm, sp);
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return 1;
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}
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@@ -1329,7 +1329,7 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
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role.level = level;
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role.direct = direct;
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if (role.direct)
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- role.glevels = 0;
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+ role.cr4_pae = 0;
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role.access = access;
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if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
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quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
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@@ -2443,7 +2443,7 @@ static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
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else
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r = paging32_init_context(vcpu);
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- vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
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+ vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
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return r;
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}
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@@ -2532,7 +2532,7 @@ static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
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}
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++vcpu->kvm->stat.mmu_pte_updated;
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- if (sp->role.glevels == PT32_ROOT_LEVEL)
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+ if (!sp->role.cr4_pae)
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paging32_update_pte(vcpu, sp, spte, new);
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else
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paging64_update_pte(vcpu, sp, spte, new);
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@@ -2681,7 +2681,7 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
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hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
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if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
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continue;
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- pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
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+ pte_size = sp->role.cr4_pae ? 8 : 4;
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misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
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misaligned |= bytes < 4;
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if (misaligned || flooded) {
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@@ -2705,7 +2705,7 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
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page_offset = offset;
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level = sp->role.level;
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npte = 1;
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- if (sp->role.glevels == PT32_ROOT_LEVEL) {
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+ if (!sp->role.cr4_pae) {
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page_offset <<= 1; /* 32->64 */
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/*
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* A 32-bit pde maps 4MB while the shadow pdes map
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