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@@ -180,7 +180,6 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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u32 mask2 = 0;
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struct ath9k_hw_capabilities *pCap = &ah->caps;
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struct ath_common *common = ath9k_hw_common(ah);
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- struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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u32 sync_cause = 0, async_cause;
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async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
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@@ -302,32 +301,8 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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ar9003_hw_bb_watchdog_read(ah);
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}
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- if (async_cause & AR_INTR_ASYNC_MASK_MCI) {
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- u32 raw_intr, rx_msg_intr;
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-
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- rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
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- raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
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-
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- if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef))
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- ath_dbg(common, MCI,
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- "MCI gets 0xdeadbeef during MCI int processing new raw_intr=0x%08x, new rx_msg_raw=0x%08x, raw_intr=0x%08x, rx_msg_raw=0x%08x\n",
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- raw_intr, rx_msg_intr, mci->raw_intr,
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- mci->rx_msg_intr);
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- else {
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- mci->rx_msg_intr |= rx_msg_intr;
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- mci->raw_intr |= raw_intr;
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- *masked |= ATH9K_INT_MCI;
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-
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- if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
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- mci->cont_status =
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- REG_READ(ah, AR_MCI_CONT_STATUS);
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-
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- REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
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- REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
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- ath_dbg(common, MCI, "AR_INTR_SYNC_MCI\n");
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-
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- }
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- }
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+ if (async_cause & AR_INTR_ASYNC_MASK_MCI)
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+ ar9003_mci_get_isr(ah, masked);
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if (sync_cause) {
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if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
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