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@@ -32,6 +32,28 @@
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static void radeon_pm_idle_work_handler(struct work_struct *work);
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static int radeon_debugfs_pm_init(struct radeon_device *rdev);
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+static void radeon_unmap_vram_bos(struct radeon_device *rdev)
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+{
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+ struct radeon_bo *bo, *n;
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+
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+ if (list_empty(&rdev->gem.objects))
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+ return;
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+
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+ list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
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+ if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
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+ ttm_bo_unmap_virtual(&bo->tbo);
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+ }
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+
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+ if (rdev->gart.table.vram.robj)
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+ ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
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+
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+ if (rdev->stollen_vga_memory)
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+ ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
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+
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+ if (rdev->r600_blit.shader_obj)
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+ ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
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+}
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+
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static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
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{
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int i;
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@@ -48,6 +70,10 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
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rdev->irq.gui_idle = false;
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radeon_irq_set(rdev);
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+ mutex_lock(&rdev->vram_mutex);
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+
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+ radeon_unmap_vram_bos(rdev);
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+
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if (!static_switch) {
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for (i = 0; i < rdev->num_crtc; i++) {
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if (rdev->pm.active_crtcs & (1 << i)) {
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@@ -67,6 +93,8 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
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}
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}
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}
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+
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+ mutex_unlock(&rdev->vram_mutex);
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/* update display watermarks based on new power state */
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radeon_update_bandwidth_info(rdev);
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