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@@ -417,8 +417,9 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
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return -EBUSY;
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}
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-static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
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+static void radeon_init_pipes(struct drm_device *dev)
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{
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+ drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t gb_tile_config, gb_pipe_sel = 0;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
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@@ -436,11 +437,12 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
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dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
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} else {
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/* R3xx */
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- if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
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+ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
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+ dev->pdev->device != 0x4144) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
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dev_priv->num_gb_pipes = 2;
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} else {
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- /* R3Vxx */
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+ /* RV3xx/R300 AD */
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dev_priv->num_gb_pipes = 1;
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}
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}
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@@ -736,7 +738,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
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/* setup the raster pipes */
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
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- radeon_init_pipes(dev_priv);
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+ radeon_init_pipes(dev);
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/* Reset the CP ring */
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radeon_do_cp_reset(dev_priv);
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