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@@ -26,6 +26,9 @@
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#define TEGRA_IRAM_BASE 0x40000000
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#define TEGRA_IRAM_BASE 0x40000000
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#define TEGRA_IRAM_SIZE SZ_256K
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#define TEGRA_IRAM_SIZE SZ_256K
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+#define TEGRA_HOST1X_BASE 0x50000000
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+#define TEGRA_HOST1X_SIZE 0x24000
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+
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#define TEGRA_ARM_PERIF_BASE 0x50040000
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#define TEGRA_ARM_PERIF_BASE 0x50040000
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#define TEGRA_ARM_PERIF_SIZE SZ_8K
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#define TEGRA_ARM_PERIF_SIZE SZ_8K
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@@ -35,12 +38,30 @@
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#define TEGRA_ARM_INT_DIST_BASE 0x50041000
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#define TEGRA_ARM_INT_DIST_BASE 0x50041000
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#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
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#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
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+#define TEGRA_MPE_BASE 0x54040000
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+#define TEGRA_MPE_SIZE SZ_256K
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+
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+#define TEGRA_VI_BASE 0x54080000
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+#define TEGRA_VI_SIZE SZ_256K
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+
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+#define TEGRA_ISP_BASE 0x54100000
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+#define TEGRA_ISP_SIZE SZ_256K
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+
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#define TEGRA_DISPLAY_BASE 0x54200000
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#define TEGRA_DISPLAY_BASE 0x54200000
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#define TEGRA_DISPLAY_SIZE SZ_256K
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#define TEGRA_DISPLAY_SIZE SZ_256K
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#define TEGRA_DISPLAY2_BASE 0x54240000
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#define TEGRA_DISPLAY2_BASE 0x54240000
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#define TEGRA_DISPLAY2_SIZE SZ_256K
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#define TEGRA_DISPLAY2_SIZE SZ_256K
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+#define TEGRA_HDMI_BASE 0x54280000
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+#define TEGRA_HDMI_SIZE SZ_256K
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+
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+#define TEGRA_GART_BASE 0x58000000
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+#define TEGRA_GART_SIZE SZ_32M
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+
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+#define TEGRA_RES_SEMA_BASE 0x60001000
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+#define TEGRA_RES_SEMA_SIZE SZ_4K
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+
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#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
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#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
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#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
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#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
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@@ -140,6 +161,18 @@
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#define TEGRA_PWFM_BASE 0x7000A000
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#define TEGRA_PWFM_BASE 0x7000A000
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#define TEGRA_PWFM_SIZE SZ_256
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#define TEGRA_PWFM_SIZE SZ_256
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+#define TEGRA_PWFM0_BASE 0x7000A000
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+#define TEGRA_PWFM0_SIZE 4
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+
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+#define TEGRA_PWFM1_BASE 0x7000A010
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+#define TEGRA_PWFM1_SIZE 4
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+
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+#define TEGRA_PWFM2_BASE 0x7000A020
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+#define TEGRA_PWFM2_SIZE 4
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+
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+#define TEGRA_PWFM3_BASE 0x7000A030
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+#define TEGRA_PWFM3_SIZE 4
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+
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#define TEGRA_MIPI_BASE 0x7000B000
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#define TEGRA_MIPI_BASE 0x7000B000
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#define TEGRA_MIPI_SIZE SZ_256
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#define TEGRA_MIPI_SIZE SZ_256
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