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@@ -48,6 +48,7 @@ static u32 tegra_lp0_wake_level_any;
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static void (*tegra_gic_mask_irq)(struct irq_data *d);
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static void (*tegra_gic_unmask_irq)(struct irq_data *d);
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+static void (*tegra_gic_ack_irq)(struct irq_data *d);
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/* ensures that sufficient time is passed for a register write to
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* serialize into the 32KHz domain */
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@@ -112,10 +113,24 @@ static void tegra_unmask(struct irq_data *d)
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tegra_legacy_unmask_irq(d->irq);
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}
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+static void tegra_ack(struct irq_data *d)
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+{
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+ tegra_legacy_force_irq_clr(d->irq);
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+ tegra_gic_ack_irq(d);
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+}
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+
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+static int tegra_retrigger(struct irq_data *d)
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+{
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+ tegra_legacy_force_irq_set(d->irq);
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+ return 1;
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+}
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+
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static struct irq_chip tegra_irq = {
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.name = "PPI",
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+ .irq_ack = tegra_ack,
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.irq_mask = tegra_mask,
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.irq_unmask = tegra_unmask,
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+ .irq_retrigger = tegra_retrigger,
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};
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void __init tegra_init_irq(void)
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@@ -132,7 +147,7 @@ void __init tegra_init_irq(void)
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gic = get_irq_chip(29);
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tegra_gic_unmask_irq = gic->irq_unmask;
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tegra_gic_mask_irq = gic->irq_mask;
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- tegra_irq.irq_ack = gic->irq_ack;
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+ tegra_gic_ack_irq = gic->irq_ack;
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#ifdef CONFIG_SMP
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tegra_irq.irq_set_affinity = gic->irq_set_affinity;
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#endif
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