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@@ -552,7 +552,7 @@ static void lpphy_2062_init(struct b43_wldev *dev)
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B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
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B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
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B43_WARN_ON(crystalfreq == 0);
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B43_WARN_ON(crystalfreq == 0);
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- if (crystalfreq >= 30000000) {
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+ if (crystalfreq <= 30000000) {
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lpphy->pdiv = 1;
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lpphy->pdiv = 1;
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b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
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b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
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} else {
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} else {
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@@ -560,14 +560,16 @@ static void lpphy_2062_init(struct b43_wldev *dev)
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b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
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b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
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}
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}
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- tmp = (800000000 * lpphy->pdiv + crystalfreq) /
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- (32000000 * lpphy->pdiv);
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- tmp = (tmp - 1) & 0xFF;
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+ tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
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+ (2 * crystalfreq)) - 8) & 0xFF;
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+ b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
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+
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+ tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
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+ (32000000 * lpphy->pdiv)) - 1) & 0xFF;
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b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
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b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
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- tmp = (2 * crystalfreq + 1000000 * lpphy->pdiv) /
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- (2000000 * lpphy->pdiv);
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- tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
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+ tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
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+ (2000000 * lpphy->pdiv)) - 1) & 0xFF;
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b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
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b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
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ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
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ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
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@@ -671,7 +673,7 @@ static void lpphy_radio_init(struct b43_wldev *dev)
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b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
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b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
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udelay(1);
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udelay(1);
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- if (dev->phy.rev < 2) {
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+ if (dev->phy.radio_ver == 0x2062) {
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lpphy_2062_init(dev);
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lpphy_2062_init(dev);
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} else {
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} else {
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lpphy_2063_init(dev);
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lpphy_2063_init(dev);
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@@ -688,11 +690,18 @@ struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
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static void lpphy_set_rc_cap(struct b43_wldev *dev)
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static void lpphy_set_rc_cap(struct b43_wldev *dev)
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{
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{
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- u8 rc_cap = dev->phy.lp->rc_cap;
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+ struct b43_phy_lp *lpphy = dev->phy.lp;
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+
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+ u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
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- b43_radio_write(dev, B2062_N_RXBB_CALIB2, max_t(u8, rc_cap-4, 0x80));
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- b43_radio_write(dev, B2062_N_TX_CTL_A, ((rc_cap & 0x1F) >> 1) | 0x80);
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- b43_radio_write(dev, B2062_S_RXG_CNT16, ((rc_cap & 0x1F) >> 2) | 0x80);
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+ if (dev->phy.rev == 1) //FIXME check channel 14!
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+ rc_cap = max_t(u8, rc_cap + 5, 15);
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+
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+ b43_radio_write(dev, B2062_N_RXBB_CALIB2,
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+ max_t(u8, lpphy->rc_cap - 4, 0x80));
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+ b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
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+ b43_radio_write(dev, B2062_S_RXG_CNT16,
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+ ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
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}
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}
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static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
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static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
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@@ -1101,6 +1110,9 @@ static void lpphy_set_tx_power_control(struct b43_wldev *dev,
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lpphy_write_tx_pctl_mode_to_hardware(dev);
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lpphy_write_tx_pctl_mode_to_hardware(dev);
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}
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}
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+static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
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+ unsigned int new_channel);
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+
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static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
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static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
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{
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{
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struct b43_phy_lp *lpphy = dev->phy.lp;
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struct b43_phy_lp *lpphy = dev->phy.lp;
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@@ -1118,11 +1130,16 @@ static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
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old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
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old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
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enum b43_lpphy_txpctl_mode old_txpctl;
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enum b43_lpphy_txpctl_mode old_txpctl;
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u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
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u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
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- int loopback, i, j, inner_sum;
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+ int loopback, i, j, inner_sum, err;
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memset(&iq_est, 0, sizeof(iq_est));
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memset(&iq_est, 0, sizeof(iq_est));
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- b43_switch_channel(dev, 7);
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+ err = b43_lpphy_op_switch_channel(dev, 7);
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+ if (err) {
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+ b43dbg(dev->wl,
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+ "RC calib: Failed to switch to channel 7, error = %d",
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+ err);
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+ }
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old_txg_ovr = (b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) >> 6) & 1;
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old_txg_ovr = (b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) >> 6) & 1;
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old_bbmult = lpphy_get_bb_mult(dev);
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old_bbmult = lpphy_get_bb_mult(dev);
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if (old_txg_ovr)
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if (old_txg_ovr)
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@@ -1881,14 +1898,14 @@ static int lpphy_b2062_tune(struct b43_wldev *dev,
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{
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{
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struct b43_phy_lp *lpphy = dev->phy.lp;
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struct b43_phy_lp *lpphy = dev->phy.lp;
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struct ssb_bus *bus = dev->dev->bus;
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struct ssb_bus *bus = dev->dev->bus;
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- static const struct b206x_channel *chandata = NULL;
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+ const struct b206x_channel *chandata = NULL;
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u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
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u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
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u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
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u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
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int i, err = 0;
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int i, err = 0;
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- for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
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- if (b2063_chantbl[i].channel == channel) {
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- chandata = &b2063_chantbl[i];
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+ for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
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+ if (b2062_chantbl[i].channel == channel) {
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+ chandata = &b2062_chantbl[i];
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break;
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break;
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}
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}
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}
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}
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