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@@ -5190,7 +5190,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
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else
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val |= PIPECONF_PROGRESSIVE;
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- if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
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+ if (intel_crtc->config.limited_color_range)
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val |= PIPECONF_COLOR_RANGE_SELECT;
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else
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val &= ~PIPECONF_COLOR_RANGE_SELECT;
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@@ -5206,8 +5206,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
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* is supported, but eventually this should handle various
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* RGB<->YCbCr scenarios as well.
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*/
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-static void intel_set_pipe_csc(struct drm_crtc *crtc,
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- const struct drm_display_mode *adjusted_mode)
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+static void intel_set_pipe_csc(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -5222,7 +5221,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc,
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* consideration.
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*/
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- if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
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+ if (intel_crtc->config.limited_color_range)
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coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
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/*
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@@ -5246,7 +5245,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc,
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if (INTEL_INFO(dev)->gen > 6) {
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uint16_t postoff = 0;
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- if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
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+ if (intel_crtc->config.limited_color_range)
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postoff = (16 * (1 << 13) / 255) & 0x1fff;
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I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
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@@ -5257,7 +5256,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc,
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} else {
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uint32_t mode = CSC_MODE_YUV_TO_RGB;
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- if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
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+ if (intel_crtc->config.limited_color_range)
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mode |= CSC_BLACK_SCREEN_OFFSET;
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I915_WRITE(PIPE_CSC_MODE(pipe), mode);
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@@ -5853,7 +5852,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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haswell_set_pipeconf(crtc, adjusted_mode, dither);
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- intel_set_pipe_csc(crtc, adjusted_mode);
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+ intel_set_pipe_csc(crtc);
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/* Set up the display plane register */
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I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
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