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@@ -38,6 +38,32 @@ static unsigned int armdiv[8] = {
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[7] = 8,
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};
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+static struct clksrc_clk hsspi_eplldiv = {
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+ .clk = {
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+ .name = "hsspi-eplldiv",
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+ .parent = &clk_esysclk.clk,
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+ .ctrlbit = (1 << 14),
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+ .enable = s3c2443_clkcon_enable_s,
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+ },
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+ .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
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+};
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+
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+static struct clk *hsspi_sources[] = {
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+ [0] = &hsspi_eplldiv.clk,
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+ [1] = NULL, /* to fix */
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+};
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+
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+static struct clksrc_clk hsspi_mux = {
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+ .clk = {
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+ .name = "hsspi-if",
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+ },
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+ .sources = &(struct clksrc_sources) {
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+ .sources = hsspi_sources,
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+ .nr_sources = ARRAY_SIZE(hsspi_sources),
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+ },
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+ .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
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+};
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+
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static struct clksrc_clk hsmmc_div[] = {
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[0] = {
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.clk = {
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@@ -114,6 +140,8 @@ void __init_or_cpufreq s3c2416_setup_clocks(void)
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static struct clksrc_clk *clksrcs[] __initdata = {
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+ &hsspi_eplldiv,
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+ &hsspi_mux,
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&hsmmc_div[0],
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&hsmmc_div[1],
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&hsmmc_mux[0],
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