|
@@ -90,26 +90,13 @@ static inline u32 ehci_read(void __iomem *base, u32 reg)
|
|
|
static int omap_ehci_init(struct usb_hcd *hcd)
|
|
|
{
|
|
|
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
|
|
- struct omap_hcd *omap = (struct omap_hcd *)ehci->priv;
|
|
|
- int rc, i;
|
|
|
-
|
|
|
- /* Hold PHYs in reset while initializing EHCI controller */
|
|
|
- for (i = 0; i < omap->nports; i++) {
|
|
|
- if (omap->phy[i])
|
|
|
- usb_phy_shutdown(omap->phy[i]);
|
|
|
- }
|
|
|
+ int rc;
|
|
|
|
|
|
/* we know this is the memory we want, no need to ioremap again */
|
|
|
ehci->caps = hcd->regs;
|
|
|
|
|
|
rc = ehci_setup(hcd);
|
|
|
|
|
|
- /* Bring PHYs out of reset */
|
|
|
- for (i = 0; i < omap->nports; i++) {
|
|
|
- if (omap->phy[i])
|
|
|
- usb_phy_init(omap->phy[i]);
|
|
|
- }
|
|
|
-
|
|
|
return rc;
|
|
|
}
|
|
|
|
|
@@ -219,9 +206,6 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
|
|
|
}
|
|
|
|
|
|
omap->phy[i] = phy;
|
|
|
- usb_phy_init(omap->phy[i]);
|
|
|
- /* bring PHY out of suspend */
|
|
|
- usb_phy_set_suspend(omap->phy[i], 0);
|
|
|
}
|
|
|
|
|
|
pm_runtime_enable(dev);
|
|
@@ -245,6 +229,20 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
|
|
|
goto err_pm_runtime;
|
|
|
}
|
|
|
|
|
|
+ /*
|
|
|
+ * Bring PHYs out of reset.
|
|
|
+ * Even though HSIC mode is a PHY-less mode, the reset
|
|
|
+ * line exists between the chips and can be modelled
|
|
|
+ * as a PHY device for reset control.
|
|
|
+ */
|
|
|
+ for (i = 0; i < omap->nports; i++) {
|
|
|
+ if (!omap->phy[i])
|
|
|
+ continue;
|
|
|
+
|
|
|
+ usb_phy_init(omap->phy[i]);
|
|
|
+ /* bring PHY out of suspend */
|
|
|
+ usb_phy_set_suspend(omap->phy[i], 0);
|
|
|
+ }
|
|
|
|
|
|
return 0;
|
|
|
|