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@@ -17,148 +17,13 @@
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#include <asm/mmu_context.h>
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#include <asm/apic.h>
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#include <asm/proto.h>
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+#include <asm/ipi.h>
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#ifdef CONFIG_X86_32
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-#include <asm/genapic.h>
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-
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-/*
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- * the following functions deal with sending IPIs between CPUs.
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- *
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- * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
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- */
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-
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-static inline int __prepare_ICR(unsigned int shortcut, int vector)
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-{
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- unsigned int icr = shortcut | apic->dest_logical;
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-
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- switch (vector) {
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- default:
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- icr |= APIC_DM_FIXED | vector;
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- break;
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- case NMI_VECTOR:
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- icr |= APIC_DM_NMI;
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- break;
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- }
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- return icr;
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-}
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-
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-static inline int __prepare_ICR2(unsigned int mask)
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-{
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- return SET_APIC_DEST_FIELD(mask);
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-}
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-
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-void __default_send_IPI_shortcut(unsigned int shortcut, int vector)
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-{
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- /*
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- * Subtle. In the case of the 'never do double writes' workaround
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- * we have to lock out interrupts to be safe. As we don't care
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- * of the value read we use an atomic rmw access to avoid costly
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- * cli/sti. Otherwise we use an even cheaper single atomic write
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- * to the APIC.
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- */
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- unsigned int cfg;
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-
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- /*
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- * Wait for idle.
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- */
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- apic_wait_icr_idle();
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-
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- /*
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- * No need to touch the target chip field
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- */
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- cfg = __prepare_ICR(shortcut, vector);
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-
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- /*
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- * Send the IPI. The write to APIC_ICR fires this off.
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- */
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- apic_write(APIC_ICR, cfg);
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-}
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void default_send_IPI_self(int vector)
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{
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- __default_send_IPI_shortcut(APIC_DEST_SELF, vector);
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-}
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-
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-/*
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- * This is used to send an IPI with no shorthand notation (the destination is
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- * specified in bits 56 to 63 of the ICR).
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- */
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-static inline void __default_send_IPI_dest_field(unsigned long mask, int vector)
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-{
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- unsigned long cfg;
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-
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- /*
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- * Wait for idle.
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- */
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- if (unlikely(vector == NMI_VECTOR))
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- safe_apic_wait_icr_idle();
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- else
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- apic_wait_icr_idle();
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-
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- /*
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- * prepare target chip field
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- */
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- cfg = __prepare_ICR2(mask);
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- apic_write(APIC_ICR2, cfg);
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-
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- /*
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- * program the ICR
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- */
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- cfg = __prepare_ICR(0, vector);
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-
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- /*
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- * Send the IPI. The write to APIC_ICR fires this off.
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- */
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- apic_write(APIC_ICR, cfg);
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-}
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-
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-/*
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- * This is only used on smaller machines.
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- */
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-void default_send_IPI_mask_bitmask(const struct cpumask *cpumask, int vector)
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-{
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- unsigned long mask = cpumask_bits(cpumask)[0];
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- unsigned long flags;
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-
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- local_irq_save(flags);
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- WARN_ON(mask & ~cpumask_bits(cpu_online_mask)[0]);
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- __default_send_IPI_dest_field(mask, vector);
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- local_irq_restore(flags);
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-}
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-
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-void default_send_IPI_mask_sequence(const struct cpumask *mask, int vector)
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-{
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- unsigned long flags;
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- unsigned int query_cpu;
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-
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- /*
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- * Hack. The clustered APIC addressing mode doesn't allow us to send
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- * to an arbitrary mask, so I do a unicasts to each CPU instead. This
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- * should be modified to do 1 message per cluster ID - mbligh
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- */
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-
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- local_irq_save(flags);
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- for_each_cpu(query_cpu, mask)
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- __default_send_IPI_dest_field(apic->cpu_to_logical_apicid(query_cpu), vector);
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- local_irq_restore(flags);
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-}
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-
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-void default_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
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-{
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- unsigned long flags;
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- unsigned int query_cpu;
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- unsigned int this_cpu = smp_processor_id();
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-
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- /* See Hack comment above */
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-
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- local_irq_save(flags);
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- for_each_cpu(query_cpu, mask) {
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- if (query_cpu == this_cpu)
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- continue;
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- __default_send_IPI_dest_field(
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- apic->cpu_to_logical_apicid(query_cpu), vector);
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- }
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- local_irq_restore(flags);
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+ __default_send_IPI_shortcut(APIC_DEST_SELF, vector, apic->dest_logical);
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}
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/* must come after the send_IPI functions above for inlining */
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