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@@ -1,7 +1,7 @@
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/*
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*
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* Copyright (C) 2007 Google, Inc.
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- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
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+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@@ -26,9 +26,7 @@
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#include <asm/localtimer.h>
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#include <asm/sched_clock.h>
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-#include <mach/msm_iomap.h>
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-#include <mach/cpu.h>
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-#include <mach/board.h>
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+#include "common.h"
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#define TIMER_MATCH_VAL 0x0000
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#define TIMER_COUNT_VAL 0x0004
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@@ -36,7 +34,7 @@
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#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
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#define TIMER_ENABLE_EN BIT(0)
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#define TIMER_CLEAR 0x000C
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-#define DGT_CLK_CTL 0x0034
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+#define DGT_CLK_CTL 0x0030
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#define DGT_CLK_CTL_DIV_4 0x3
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#define GPT_HZ 32768
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@@ -172,44 +170,21 @@ static notrace u32 msm_sched_clock_read(void)
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return msm_clocksource.read(&msm_clocksource);
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}
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-static void __init msm_timer_init(void)
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+static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
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+ bool percpu)
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{
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struct clock_event_device *ce = &msm_clockevent;
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struct clocksource *cs = &msm_clocksource;
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int res;
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- u32 dgt_hz;
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-
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- if (cpu_is_msm7x01()) {
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- event_base = MSM_CSR_BASE;
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- source_base = MSM_CSR_BASE + 0x10;
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- dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
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- cs->read = msm_read_timer_count_shift;
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- cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
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- } else if (cpu_is_msm7x30()) {
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- event_base = MSM_CSR_BASE + 0x04;
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- source_base = MSM_CSR_BASE + 0x24;
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- dgt_hz = 24576000 / 4;
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- } else if (cpu_is_qsd8x50()) {
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- event_base = MSM_CSR_BASE;
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- source_base = MSM_CSR_BASE + 0x10;
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- dgt_hz = 19200000 / 4;
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- } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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- event_base = MSM_TMR_BASE + 0x04;
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- /* Use CPU0's timer as the global clock source. */
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- source_base = MSM_TMR0_BASE + 0x24;
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- dgt_hz = 27000000 / 4;
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- writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
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- } else
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- BUG();
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writel_relaxed(0, event_base + TIMER_ENABLE);
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
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ce->cpumask = cpumask_of(0);
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+ ce->irq = irq;
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- ce->irq = INT_GP_TIMER_EXP;
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clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
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- if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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+ if (percpu) {
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msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
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if (!msm_evt.percpu_evt) {
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pr_err("memory allocation failed for %s\n", ce->name);
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@@ -238,10 +213,83 @@ err:
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res = clocksource_register_hz(cs, dgt_hz);
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if (res)
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pr_err("clocksource_register failed\n");
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- setup_sched_clock(msm_sched_clock_read,
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- cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
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+ setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
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}
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-struct sys_timer msm_timer = {
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- .init = msm_timer_init
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+static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
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+{
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+ event_base = ioremap(event, SZ_64);
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+ if (!event_base) {
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+ pr_err("Failed to map event base\n");
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+ return 1;
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+ }
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+ source_base = ioremap(source, SZ_64);
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+ if (!source_base) {
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+ pr_err("Failed to map source base\n");
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+ return 1;
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+ }
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+ return 0;
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+}
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+
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+static void __init msm7x01_timer_init(void)
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+{
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+ struct clocksource *cs = &msm_clocksource;
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+
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+ if (msm_timer_map(0xc0100000, 0xc0100010))
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+ return;
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+ cs->read = msm_read_timer_count_shift;
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+ cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
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+ /* 600 KHz */
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+ msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
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+ false);
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+}
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+
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+struct sys_timer msm7x01_timer = {
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+ .init = msm7x01_timer_init
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+};
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+
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+static void __init msm7x30_timer_init(void)
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+{
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+ if (msm_timer_map(0xc0100004, 0xc0100024))
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+ return;
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+ msm_timer_init(24576000 / 4, 32, 1, false);
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+}
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+
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+struct sys_timer msm7x30_timer = {
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+ .init = msm7x30_timer_init
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+};
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+
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+static void __init msm8x60_timer_init(void)
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+{
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+ if (msm_timer_map(0x02000004, 0x02040024))
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+ return;
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+ writel_relaxed(DGT_CLK_CTL_DIV_4, event_base + DGT_CLK_CTL);
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+ msm_timer_init(27000000 / 4, 32, 17, true);
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+}
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+
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+struct sys_timer msm8x60_timer = {
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+ .init = msm8x60_timer_init
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+};
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+
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+static void __init msm8960_timer_init(void)
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+{
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+ if (msm_timer_map(0x0200A004, 0x0208A024))
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+ return;
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+ writel_relaxed(DGT_CLK_CTL_DIV_4, event_base + DGT_CLK_CTL);
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+ msm_timer_init(27000000 / 4, 32, 17, true);
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+}
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+
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+struct sys_timer msm8960_timer = {
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+ .init = msm8960_timer_init
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+};
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+
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+static void __init qsd8x50_timer_init(void)
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+{
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+ if (msm_timer_map(0xAC100000, 0xAC100010))
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+ return;
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+ msm_timer_init(19200000 / 4, 32, 7, false);
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+}
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+
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+struct sys_timer qsd8x50_timer = {
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+ .init = qsd8x50_timer_init
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};
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Stephen Boyd