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@@ -665,6 +665,30 @@ config X86_VISWS_APIC
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def_bool y
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depends on X86_32 && X86_VISWS
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+config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
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+ bool "Reroute for broken boot IRQs"
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+ default n
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+ depends on X86_IO_APIC
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+ help
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+ This option enables a workaround that fixes a source of
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+ spurious interrupts. This is recommended when threaded
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+ interrupt handling is used on systems where the generation of
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+ superfluous "boot interrupts" cannot be disabled.
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+
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+ Some chipsets generate a legacy INTx "boot IRQ" when the IRQ
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+ entry in the chipset's IO-APIC is masked (as, e.g. the RT
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+ kernel does during interrupt handling). On chipsets where this
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+ boot IRQ generation cannot be disabled, this workaround keeps
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+ the original IRQ line masked so that only the equivalent "boot
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+ IRQ" is delivered to the CPUs. The workaround also tells the
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+ kernel to set up the IRQ handler on the boot IRQ line. In this
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+ way only one interrupt is delivered to the kernel. Otherwise
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+ the spurious second interrupt may cause the kernel to bring
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+ down (vital) interrupt lines.
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+
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+ Only affects "broken" chipsets. Interrupt sharing may be
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+ increased on these systems.
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+
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config X86_MCE
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bool "Machine Check Exception"
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depends on !X86_VOYAGER
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