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@@ -422,7 +422,6 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
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static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
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enum dev_state state)
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{
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- int mask = (state == STATE_RADIO_IRQ_ON);
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u32 reg;
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unsigned long flags;
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@@ -436,25 +435,14 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
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}
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spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
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- rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
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- rt2x00_set_field32(®, INT_MASK_CSR_RXDELAYINT, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_TXDELAYINT, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, mask);
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- rt2x00_set_field32(®, INT_MASK_CSR_AC0_DMA_DONE, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_AC1_DMA_DONE, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_AC2_DMA_DONE, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_AC3_DMA_DONE, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_HCCA_DMA_DONE, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_MGMT_DMA_DONE, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_MCU_COMMAND, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_RXTX_COHERENT, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_TBTT, mask);
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- rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, mask);
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- rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, mask);
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- rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, mask);
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- rt2x00_set_field32(®, INT_MASK_CSR_GPTIMER, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_RX_COHERENT, 0);
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- rt2x00_set_field32(®, INT_MASK_CSR_TX_COHERENT, 0);
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+ reg = 0;
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+ if (state == STATE_RADIO_IRQ_ON) {
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+ rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1);
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+ rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1);
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+ rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1);
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+ rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
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+ rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
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+ }
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rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
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spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
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