drm/i915: kill per-ring macros

Two macros that use a base address for HWS_PGA were missing, add them.
Also switch the remaining users of *_ACTHD to the ring-base one.
Kill the other ring-specific macros because they're now unused.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[ickle: And silence checkpatch whilst in the vicinity]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

drivers/gpu/drm/i915/i915_reg.h

@@ -253,11 +253,13 @@
 #define RENDER_RING_BASE	0x02000
 #define BSD_RING_BASE		0x04000
 #define GEN6_BSD_RING_BASE	0x12000
-#define RING_TAIL(base)		(base)+0x30
-#define RING_HEAD(base)		(base)+0x34
-#define RING_START(base)	(base)+0x38
-#define RING_CTL(base)		(base)+0x3c
-#define RING_HWS_PGA(base)	(base)+0x80
+#define RING_TAIL(base)		((base)+0x30)
+#define RING_HEAD(base)		((base)+0x34)
+#define RING_START(base)	((base)+0x38)
+#define RING_CTL(base)		((base)+0x3c)
+#define RING_HWS_PGA(base)	((base)+0x80)
+#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
+#define RING_ACTHD(base)	((base)+0x74)
 #define   TAIL_ADDR		0x001FFFF8
 #define   HEAD_WRAP_COUNT	0xFFE00000
 #define   HEAD_WRAP_ONE		0x00200000
@@ -283,7 +285,6 @@
 #define INSTDONE1	0x0207c /* 965+ only */
 #define ACTHD_I965	0x02074
 #define HWS_PGA		0x02080
-#define HWS_PGA_GEN6	0x04080
 #define HWS_ADDRESS_MASK	0xfffff000
 #define HWS_START_ADDRESS_SHIFT	4
 #define PWRCTXA		0x2088 /* 965GM+ only */
@@ -441,28 +442,6 @@
 #define   GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR	(1 << 25)
 #define   GEN6_BLITTER_SYNC_STATUS			(1 << 24)
 #define   GEN6_BLITTER_USER_INTERRUPT			(1 << 22)
-/*
- * BSD (bit stream decoder instruction and interrupt control register defines
- * (G4X and Ironlake only)
- */
-
-#define BSD_RING_TAIL          0x04030
-#define BSD_RING_HEAD          0x04034
-#define BSD_RING_START         0x04038
-#define BSD_RING_CTL           0x0403c
-#define BSD_RING_ACTHD         0x04074
-#define BSD_HWS_PGA            0x04080
-
-/*
- * video command stream instruction and interrupt control register defines
- * for GEN6
- */
-#define GEN6_BSD_RING_TAIL		0x12030
-#define GEN6_BSD_RING_HEAD		0x12034
-#define GEN6_BSD_RING_START		0x12038
-#define GEN6_BSD_RING_CTL		0x1203c
-#define GEN6_BSD_RING_ACTHD		0x12074
-#define GEN6_BSD_HWS_PGA		0x14080
 
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
 #define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK	(1 << 16)

drivers/gpu/drm/i915/intel_ringbuffer.c

@@ -131,7 +131,8 @@ static unsigned int render_ring_get_active_head(struct drm_device *dev,
 						struct intel_ring_buffer *ring)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ? ACTHD_I965 : ACTHD;
+	u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ?
+			RING_ACTHD(ring->mmio_base) : ACTHD;
 
 	return I915_READ(acthd_reg);
 }
@@ -352,11 +353,13 @@ static void render_setup_status_page(struct drm_device *dev,
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	if (IS_GEN6(dev)) {
-		I915_WRITE(HWS_PGA_GEN6, ring->status_page.gfx_addr);
-		I915_READ(HWS_PGA_GEN6); /* posting read */
+		I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base),
+			   ring->status_page.gfx_addr);
+		I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base)); /* posting read */
 	} else {
-		I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
-		I915_READ(HWS_PGA); /* posting read */
+		I915_WRITE(RING_HWS_PGA(ring->mmio_base),
+			   ring->status_page.gfx_addr);
+		I915_READ(RING_HWS_PGA(ring->mmio_base)); /* posting read */
 	}
 
 }
@@ -377,7 +380,7 @@ static unsigned int bsd_ring_get_active_head(struct drm_device *dev,
 					     struct intel_ring_buffer *ring)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	return I915_READ(BSD_RING_ACTHD);
+	return I915_READ(RING_ACTHD(ring->mmio_base));
 }
 
 static int init_bsd_ring(struct drm_device *dev,
@@ -412,8 +415,8 @@ static void bsd_setup_status_page(struct drm_device *dev,
 				  struct  intel_ring_buffer *ring)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	I915_WRITE(BSD_HWS_PGA, ring->status_page.gfx_addr);
-	I915_READ(BSD_HWS_PGA);
+	I915_WRITE(RING_HWS_PGA(ring->mmio_base), ring->status_page.gfx_addr);
+	I915_READ(RING_HWS_PGA(ring->mmio_base));
 }
 
 static void
@@ -801,8 +804,8 @@ static void gen6_bsd_setup_status_page(struct drm_device *dev,
 				       struct  intel_ring_buffer *ring)
 {
        drm_i915_private_t *dev_priv = dev->dev_private;
-       I915_WRITE(GEN6_BSD_HWS_PGA, ring->status_page.gfx_addr);
-       I915_READ(GEN6_BSD_HWS_PGA);
+       I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base), ring->status_page.gfx_addr);
+       I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base));
 }
 
 static void gen6_bsd_ring_set_tail(struct drm_device *dev,
@@ -832,7 +835,7 @@ static unsigned int gen6_bsd_ring_get_active_head(struct drm_device *dev,
 						  struct intel_ring_buffer *ring)
 {
        drm_i915_private_t *dev_priv = dev->dev_private;
-       return I915_READ(GEN6_BSD_RING_ACTHD);
+       return I915_READ(RING_ACTHD(ring->mmio_base));
 }
 
 static void gen6_bsd_ring_flush(struct drm_device *dev,