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@@ -925,6 +925,20 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
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{0x00004044, 0x00000000},
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};
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+static const u32 ar9280PciePhy_awow[][2] = {
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+ /* Addr allmodes */
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+ {0x00004040, 0x9248fd00},
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+ {0x00004040, 0x24924924},
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+ {0x00004040, 0xa8000019},
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+ {0x00004040, 0x13160820},
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+ {0x00004040, 0xe5980560},
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+ {0x00004040, 0xc01dcffd},
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+ {0x00004040, 0x1aaabe41},
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+ {0x00004040, 0xbe105554},
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+ {0x00004040, 0x00043007},
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+ {0x00004044, 0x00000000},
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+};
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+
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static const u32 ar9285Modes_9285_1_2[][5] = {
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/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
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{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
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