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@@ -40,6 +40,15 @@
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#define BCM4329_CORE_ARM_BASE 0x18002000
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#define BCM4329_RAMSIZE 0x48000
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+/* bcm43143 */
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+/* SDIO device core */
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+#define BCM43143_CORE_BUS_BASE 0x18002000
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+/* internal memory core */
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+#define BCM43143_CORE_SOCRAM_BASE 0x18004000
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+/* ARM Cortex M3 core, ID 0x82a */
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+#define BCM43143_CORE_ARM_BASE 0x18003000
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+#define BCM43143_RAMSIZE 0x70000
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+
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#define SBCOREREV(sbidh) \
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((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
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((sbidh) & SSB_IDHIGH_RCLO))
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@@ -433,6 +442,23 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
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/* Address of cores for new chips should be added here */
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switch (ci->chip) {
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+ case BCM43143_CHIP_ID:
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+ ci->c_inf[0].wrapbase = ci->c_inf[0].base + 0x00100000;
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+ ci->c_inf[0].cib = 0x2b000000;
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+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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+ ci->c_inf[1].base = BCM43143_CORE_BUS_BASE;
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+ ci->c_inf[1].wrapbase = ci->c_inf[1].base + 0x00100000;
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+ ci->c_inf[1].cib = 0x18000000;
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+ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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+ ci->c_inf[2].base = BCM43143_CORE_SOCRAM_BASE;
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+ ci->c_inf[2].wrapbase = ci->c_inf[2].base + 0x00100000;
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+ ci->c_inf[2].cib = 0x14000000;
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+ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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+ ci->c_inf[3].base = BCM43143_CORE_ARM_BASE;
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+ ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
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+ ci->c_inf[3].cib = 0x07000000;
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+ ci->ramsize = BCM43143_RAMSIZE;
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+ break;
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case BCM43241_CHIP_ID:
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ci->c_inf[0].wrapbase = 0x18100000;
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ci->c_inf[0].cib = 0x2a084411;
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