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@@ -227,9 +227,6 @@ struct i7core_dev_info {
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.dev_id = (device_id)
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struct pci_id_descr pci_devs[] = {
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- /* Generic Non-core registers */
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- { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE) },
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-
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/* Memory controller */
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{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
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{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
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@@ -253,6 +250,16 @@ struct pci_id_descr pci_devs[] = {
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{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
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{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
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{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
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+
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+ /* Generic Non-core registers */
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+ /*
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+ * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
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+ * On Xeon 55xx, however, it has a different id (8086:2c40). So,
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+ * the probing code needs to test for the other address in case of
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+ * failure of this one
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+ */
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+ { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE) },
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+
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};
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#define N_DEVS ARRAY_SIZE(pci_devs)
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@@ -1138,6 +1145,16 @@ static int i7core_get_devices(void)
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pci_devs[i].dev_id, NULL);
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}
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+ /*
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+ * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
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+ * is at addr 8086:2c40, instead of 8086:2c41. So, we need
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+ * to probe for the alternate address in case of failure
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+ */
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+ if (pci_devs[i].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE
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+ && !pdev)
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+ pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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+ PCI_DEVICE_ID_INTEL_I7_NOCORE_ALT, NULL);
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+
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if (likely(pdev)) {
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bus = pdev->bus->number;
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