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@@ -1322,12 +1322,13 @@ static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
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/*
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* According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
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* Architectures Software Developer’s Manual Volume 3B.
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- * The MCA registers are the following ones:
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+ * Nehalem are defined as family 0x06, model 0x1a
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+ *
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+ * The MCA registers used here are the following ones:
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* struct mce field MCA Register
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- * m->status MSR_IA32_MC0_STATUS
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- * m->addr MSR_IA32_MC0_ADDR
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- * m->misc MSR_IA32_MC0_MISC
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- * m->mcgstatus MSR_IA32_MCG_STATUS
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+ * m->status MSR_IA32_MC8_STATUS
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+ * m->addr MSR_IA32_MC8_ADDR
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+ * m->misc MSR_IA32_MC8_MISC
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* In the case of Nehalem, the error information is masked at .status and .misc
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* fields
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*/
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@@ -1375,10 +1376,11 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
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err = "unknown";
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}
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+ /* FIXME: should convert addr into bank and rank information */
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msg = kasprintf(GFP_ATOMIC,
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- "%s (addr = 0x%08llx Bank=0x%08x, Dimm=%d, Channel=%d, "
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- "syndrome=0x%08x total error count=%d Err=%d (%s))\n",
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- type, (long long) m->addr, m->bank, dimm, channel,
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+ "%s (addr = 0x%08llx Dimm=%d, Channel=%d, "
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+ "syndrome=0x%08x, count=%d Err=%d (%s))\n",
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+ type, (long long) m->addr, dimm, channel,
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syndrome, core_err_cnt,errnum, err);
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debugf0("%s", msg);
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@@ -1447,6 +1449,10 @@ static int i7core_mce_check_error(void *priv, struct mce *mce)
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if (((mce->status & 0xffff) >> 7) != 1)
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return 0;
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+ /* Bank 8 registers are the only ones that we know how to handle */
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+ if (mce->bank != 8)
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+ return 0;
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+
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spin_lock_irqsave(&pvt->mce_lock, flags);
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if (pvt->mce_count < MCE_LOG_LEN) {
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memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce));
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