|
@@ -126,8 +126,7 @@ enum {
|
|
|
ich6_sata = 7,
|
|
|
ich6_sata_ahci = 8,
|
|
|
ich6m_sata_ahci = 9,
|
|
|
- ich7m_sata_ahci = 10,
|
|
|
- ich8_sata_ahci = 11,
|
|
|
+ ich8_sata_ahci = 10,
|
|
|
|
|
|
/* constants for mapping table */
|
|
|
P0 = 0, /* port 0 */
|
|
@@ -169,6 +168,7 @@ static const struct pci_device_id piix_pci_tbl[] = {
|
|
|
#ifdef ATA_ENABLE_PATA
|
|
|
/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
|
|
|
/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
|
|
|
+ { 0x8086, 0x7110, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
|
|
|
{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
|
|
|
{ 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
|
{ 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
@@ -227,7 +227,7 @@ static const struct pci_device_id piix_pci_tbl[] = {
|
|
|
/* 82801GB/GR/GH (ICH7, identical to ICH6) */
|
|
|
{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
|
|
|
/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
|
|
|
- { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci },
|
|
|
+ { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
|
|
|
/* Enterprise Southbridge 2 (where's the datasheet?) */
|
|
|
{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
|
|
|
/* SATA Controller 1 IDE (ICH8, no datasheet yet) */
|
|
@@ -399,23 +399,10 @@ static const struct piix_map_db ich6m_map_db = {
|
|
|
.mask = 0x3,
|
|
|
.port_enable = 0x5,
|
|
|
.present_shift = 4,
|
|
|
- .map = {
|
|
|
- /* PM PS SM SS MAP */
|
|
|
- { P0, P2, RV, RV }, /* 00b */
|
|
|
- { RV, RV, RV, RV },
|
|
|
- { P0, P2, IDE, IDE }, /* 10b */
|
|
|
- { RV, RV, RV, RV },
|
|
|
- },
|
|
|
-};
|
|
|
-
|
|
|
-static const struct piix_map_db ich7m_map_db = {
|
|
|
- .mask = 0x3,
|
|
|
- .port_enable = 0x5,
|
|
|
- .present_shift = 4,
|
|
|
|
|
|
/* Map 01b isn't specified in the doc but some notebooks use
|
|
|
- * it anyway. ATM, the only case spotted carries subsystem ID
|
|
|
- * 1025:0107. This is the only difference from ich6m.
|
|
|
+ * it anyway. MAP 01b have been spotted on both ICH6M and
|
|
|
+ * ICH7M.
|
|
|
*/
|
|
|
.map = {
|
|
|
/* PM PS SM SS MAP */
|
|
@@ -445,7 +432,6 @@ static const struct piix_map_db *piix_map_db_table[] = {
|
|
|
[ich6_sata] = &ich6_map_db,
|
|
|
[ich6_sata_ahci] = &ich6_map_db,
|
|
|
[ich6m_sata_ahci] = &ich6m_map_db,
|
|
|
- [ich7m_sata_ahci] = &ich7m_map_db,
|
|
|
[ich8_sata_ahci] = &ich8_map_db,
|
|
|
};
|
|
|
|
|
@@ -556,19 +542,7 @@ static struct ata_port_info piix_port_info[] = {
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
},
|
|
|
|
|
|
- /* ich7m_sata_ahci: 10 */
|
|
|
- {
|
|
|
- .sht = &piix_sht,
|
|
|
- .flags = ATA_FLAG_SATA |
|
|
|
- PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
|
|
|
- PIIX_FLAG_AHCI,
|
|
|
- .pio_mask = 0x1f, /* pio0-4 */
|
|
|
- .mwdma_mask = 0x07, /* mwdma0-2 */
|
|
|
- .udma_mask = 0x7f, /* udma0-6 */
|
|
|
- .port_ops = &piix_sata_ops,
|
|
|
- },
|
|
|
-
|
|
|
- /* ich8_sata_ahci: 11 */
|
|
|
+ /* ich8_sata_ahci: 10 */
|
|
|
{
|
|
|
.sht = &piix_sht,
|
|
|
.flags = ATA_FLAG_SATA |
|