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@@ -211,6 +211,28 @@ static const struct tjmax __cpuinitconst tjmax_table[] = {
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{ "CPU CE4170", 110000 }, /* Model 0x1c, stepping 10 */
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};
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+struct tjmax_model {
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+ u8 model;
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+ u8 mask;
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+ int tjmax;
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+};
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+
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+#define ANY 0xff
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+
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+static const struct tjmax_model __cpuinitconst tjmax_model_table[] = {
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+ { 0x1c, 10, 100000 }, /* D4xx, N4xx, D5xx, N5xx */
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+ { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others
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+ * Note: Also matches 230 and 330,
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+ * which are covered by tjmax_table
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+ */
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+ { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx)
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+ * Note: TjMax for E6xxT is 110C, but CPU type
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+ * is undetectable by software
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+ */
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+ { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */
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+ { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) */
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+};
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+
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static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
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struct device *dev)
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{
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@@ -229,20 +251,11 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
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return tjmax_table[i].tjmax;
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}
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- /* Atom CPUs */
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-
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- if (c->x86_model == 0x1c) {
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- /*
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- * TjMax for stepping 10 CPUs (N4xx, N5xx, D4xx, D5xx)
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- * is 100 degrees C, for all others it is 90 degrees C.
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- */
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- if (c->x86_mask == 10)
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- return 100000;
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- return 90000;
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- } else if (c->x86_model == 0x26 || c->x86_model == 0x27) {
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- return 90000;
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- } else if (c->x86_model == 0x36) {
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- return 100000;
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+ for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
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+ const struct tjmax_model *tm = &tjmax_model_table[i];
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+ if (c->x86_model == tm->model &&
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+ (tm->mask == ANY || c->x86_mask == tm->mask))
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+ return tm->tjmax;
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}
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/* Early chips have no MSR for TjMax */
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