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@@ -937,6 +937,7 @@ struct netxen_adapter {
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struct netxen_ring_ctx *ctx_desc;
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struct pci_dev *ctx_desc_pdev;
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dma_addr_t ctx_desc_phys_addr;
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+ int intr_scheme;
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int (*enable_phy_interrupts) (struct netxen_adapter *);
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int (*disable_phy_interrupts) (struct netxen_adapter *);
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void (*handle_phy_intr) (struct netxen_adapter *);
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@@ -1080,37 +1081,106 @@ struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
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static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
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{
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- /*
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- * ISR_INT_MASK: Can be read from window 0 or 1.
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- */
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- writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
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+ uint32_t mask = 0x7ff;
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+ int retries = 32;
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+
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+ DPRINTK(1, INFO, "Entered ISR Disable \n");
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+
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+ switch (adapter->portnum) {
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+ case 0:
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+ writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
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+ break;
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+ case 1:
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+ writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
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+ break;
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+ case 2:
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+ writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
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+ break;
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+ case 3:
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+ writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
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+ break;
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+ }
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+
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+ if (adapter->intr_scheme != -1 &&
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+ adapter->intr_scheme != INTR_SCHEME_PERPORT) {
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+ writel(mask,
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+ (void *)(PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)));
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+ }
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+
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+ /* Window = 0 or 1 */
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+ if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
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+ do {
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+ writel(0xffffffff, (void *)
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+ (PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_TARGET_STATUS)));
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+ mask = readl((void *)
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+ (pci_base_offset(adapter, ISR_INT_VECTOR)));
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+ if (!(mask & 0x80))
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+ break;
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+ udelay(10);
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+ } while (--retries);
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+
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+ if (!retries) {
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+ printk(KERN_NOTICE "%s: Failed to disable interrupt completely\n",
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+ netxen_nic_driver_name);
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+ }
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+ }
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+
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+ DPRINTK(1, INFO, "Done with Disable Int\n");
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+ return;
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}
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static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
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{
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u32 mask;
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- switch (adapter->ahw.board_type) {
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- case NETXEN_NIC_GBE:
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- mask = 0x77b;
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+ DPRINTK(1, INFO, "Entered ISR Enable \n");
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+
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+ if (adapter->intr_scheme != -1 &&
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+ adapter->intr_scheme != INTR_SCHEME_PERPORT) {
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+ switch (adapter->ahw.board_type) {
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+ case NETXEN_NIC_GBE:
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+ mask = 0x77b;
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+ break;
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+ case NETXEN_NIC_XGBE:
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+ mask = 0x77f;
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+ break;
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+ default:
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+ mask = 0x7ff;
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+ break;
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+ }
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+
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+ writel(mask,
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+ (void *)(PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)));
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+ }
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+ switch (adapter->portnum) {
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+ case 0:
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+ writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
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break;
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- case NETXEN_NIC_XGBE:
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- mask = 0x77f;
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+ case 1:
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+ writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
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break;
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- default:
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- mask = 0x7ff;
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+ case 2:
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+ writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
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+ break;
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+ case 3:
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+ writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
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break;
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}
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- writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
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-
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if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
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mask = 0xbff;
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- writel(0X0, NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR));
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- writel(mask, PCI_OFFSET_SECOND_RANGE(adapter,
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- ISR_INT_TARGET_MASK));
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+ if (adapter->intr_scheme != -1 &&
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+ adapter->intr_scheme != INTR_SCHEME_PERPORT) {
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+ writel(0X0, NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR));
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+ }
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+ writel(mask,
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+ (void *)(PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_TARGET_MASK)));
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}
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+
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+ DPRINTK(1, INFO, "Done with enable Int\n");
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+
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+ return;
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}
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/*
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