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@@ -37,6 +37,8 @@
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#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
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OMAP3430_PM_PREPWSTST)
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#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
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+#define SRAM_BASE_P 0x40200000
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+#define CONTROL_STAT 0x480022F0
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#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
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* available */
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#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
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@@ -51,6 +53,40 @@ ENTRY(get_restore_pointer)
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ldmfd sp!, {pc} @ restore regs and return
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ENTRY(get_restore_pointer_sz)
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.word . - get_restore_pointer_sz
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+
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+/* Function to call rom code to save secure ram context */
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+ENTRY(save_secure_ram_context)
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+ stmfd sp!, {r1-r12, lr} @ save registers on stack
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+save_secure_ram_debug:
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+ /* b save_secure_ram_debug */ @ enable to debug save code
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+ adr r3, api_params @ r3 points to parameters
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+ str r0, [r3,#0x4] @ r0 has sdram address
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+ ldr r12, high_mask
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+ and r3, r3, r12
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+ ldr r12, sram_phy_addr_mask
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+ orr r3, r3, r12
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+ mov r0, #25 @ set service ID for PPA
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+ mov r12, r0 @ copy secure service ID in r12
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+ mov r1, #0 @ set task id for ROM code in r1
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+ mov r2, #7 @ set some flags in r2, r6
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+ mov r6, #0xff
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+ mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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+ mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
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+ .word 0xE1600071 @ call SMI monitor (smi #1)
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+ nop
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+ nop
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+ nop
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+ nop
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+ ldmfd sp!, {r1-r12, pc}
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+sram_phy_addr_mask:
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+ .word SRAM_BASE_P
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+high_mask:
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+ .word 0xffff
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+api_params:
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+ .word 0x4, 0x0, 0x0, 0x1, 0x1
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+ENTRY(save_secure_ram_context_sz)
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+ .word . - save_secure_ram_context
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+
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/*
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* Forces OMAP into idle state
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*
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@@ -107,9 +143,44 @@ restore:
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moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
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movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
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bne logic_l1_restore
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+ ldr r0, control_stat
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+ ldr r1, [r0]
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+ and r1, #0x700
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+ cmp r1, #0x300
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+ beq l2_inv_gp
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+ mov r0, #40 @ set service ID for PPA
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+ mov r12, r0 @ copy secure Service ID in r12
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+ mov r1, #0 @ set task id for ROM code in r1
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+ mov r2, #4 @ set some flags in r2, r6
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+ mov r6, #0xff
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+ adr r3, l2_inv_api_params @ r3 points to dummy parameters
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+ mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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+ mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
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+ .word 0xE1600071 @ call SMI monitor (smi #1)
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+ /* Write to Aux control register to set some bits */
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+ mov r0, #42 @ set service ID for PPA
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+ mov r12, r0 @ copy secure Service ID in r12
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+ mov r1, #0 @ set task id for ROM code in r1
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+ mov r2, #4 @ set some flags in r2, r6
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+ mov r6, #0xff
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+ adr r3, write_aux_control_params @ r3 points to parameters
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+ mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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+ mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
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+ .word 0xE1600071 @ call SMI monitor (smi #1)
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+
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+ b logic_l1_restore
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+l2_inv_api_params:
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+ .word 0x1, 0x00
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+write_aux_control_params:
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+ .word 0x1, 0x72
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+l2_inv_gp:
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/* Execute smi to invalidate L2 cache */
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mov r12, #0x1 @ set up to invalide L2
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-smi: .word 0xE1600070 @ Call SMI monitor (smieq)
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+smi: .word 0xE1600070 @ Call SMI monitor (smieq)
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+ /* Write to Aux control register to set some bits */
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+ mov r0, #0x72
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+ mov r12, #0x3
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+ .word 0xE1600070 @ Call SMI monitor (smieq)
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logic_l1_restore:
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mov r1, #0
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/* Invalidate all instruction caches to PoU
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@@ -429,5 +500,7 @@ table_entry:
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.word 0x00000C02
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cache_pred_disable_mask:
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.word 0xFFFFE7FB
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+control_stat:
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+ .word CONTROL_STAT
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ENTRY(omap34xx_cpu_suspend_sz)
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.word . - omap34xx_cpu_suspend
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