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@@ -54,6 +54,12 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
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static int enable_1510_mode;
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+static struct omap_dma_global_context_registers {
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+ u32 dma_irqenable_l0;
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+ u32 dma_ocp_sysconfig;
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+ u32 dma_gcr;
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+} omap_dma_global_context;
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+
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struct omap_dma_lch {
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int next_lch;
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int dev_id;
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@@ -2341,6 +2347,39 @@ void omap_stop_lcd_dma(void)
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}
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EXPORT_SYMBOL(omap_stop_lcd_dma);
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+void omap_dma_global_context_save(void)
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+{
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+ omap_dma_global_context.dma_irqenable_l0 =
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+ dma_read(IRQENABLE_L0);
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+ omap_dma_global_context.dma_ocp_sysconfig =
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+ dma_read(OCP_SYSCONFIG);
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+ omap_dma_global_context.dma_gcr = dma_read(GCR);
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+}
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+
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+void omap_dma_global_context_restore(void)
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+{
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+ dma_write(0x2, OCP_SYSCONFIG);
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+ while (!__raw_readl(omap_dma_base + OMAP_DMA4_SYSSTATUS))
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+ ;
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+ dma_write(omap_dma_global_context.dma_gcr, GCR);
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+ dma_write(omap_dma_global_context.dma_ocp_sysconfig,
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+ OCP_SYSCONFIG);
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+ dma_write(omap_dma_global_context.dma_irqenable_l0,
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+ IRQENABLE_L0);
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+}
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+
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+void omap_dma_disable_irq(int lch)
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+{
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+ u32 val;
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+
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+ if (cpu_class_is_omap2()) {
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+ /* Disable interrupts */
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+ val = dma_read(IRQENABLE_L0);
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+ val &= ~(1 << lch);
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+ dma_write(val, IRQENABLE_L0);
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+ }
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+}
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+
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/*----------------------------------------------------------------------------*/
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static int __init omap_init_dma(void)
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