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@@ -178,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk)
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if (!dd)
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return;
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- /* Return bypass rate if DPLL is bypassed */
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v = __raw_readl(dd->control_reg);
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v &= dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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- /* Reparent in case the dpll is in bypass */
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+ /* Reparent the struct clk in case the dpll is in bypass */
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if (cpu_is_omap24xx()) {
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if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
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v == OMAP2XXX_EN_DPLL_FRBYPASS)
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@@ -259,51 +258,23 @@ u32 omap2_get_dpll_rate(struct clk *clk)
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/* DPLL rate rounding code */
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-/**
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- * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
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- * @clk: struct clk * of the DPLL
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- * @tolerance: maximum rate error tolerance
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- *
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- * Set the maximum DPLL rate error tolerance for the rate rounding
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- * algorithm. The rate tolerance is an attempt to balance DPLL power
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- * saving (the least divider value "n") vs. rate fidelity (the least
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- * difference between the desired DPLL target rate and the rounded
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- * rate out of the algorithm). So, increasing the tolerance is likely
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- * to decrease DPLL power consumption and increase DPLL rate error.
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- * Returns -EINVAL if provided a null clock ptr or a clk that is not a
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- * DPLL; or 0 upon success.
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- */
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-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
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-{
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- if (!clk || !clk->dpll_data)
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- return -EINVAL;
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-
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- clk->dpll_data->rate_tolerance = tolerance;
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-
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- return 0;
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-}
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-
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/**
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* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
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* @clk: struct clk * for a DPLL
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* @target_rate: desired DPLL clock rate
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*
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- * Given a DPLL, a desired target rate, and a rate tolerance, round
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- * the target rate to a possible, programmable rate for this DPLL.
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- * Rate tolerance is assumed to be set by the caller before this
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- * function is called. Attempts to select the minimum possible n
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- * within the tolerance to reduce power consumption. Stores the
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- * computed (m, n) in the DPLL's dpll_data structure so set_rate()
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- * will not need to call this (expensive) function again. Returns ~0
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- * if the target rate cannot be rounded, either because the rate is
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- * too low or because the rate tolerance is set too tightly; or the
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- * rounded rate upon success.
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+ * Given a DPLL and a desired target rate, round the target rate to a
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+ * possible, programmable rate for this DPLL. Attempts to select the
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+ * minimum possible n. Stores the computed (m, n) in the DPLL's
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+ * dpll_data structure so set_rate() will not need to call this
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+ * (expensive) function again. Returns ~0 if the target rate cannot
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+ * be rounded, or the rounded rate upon success.
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*/
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long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
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{
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- int m, n, r, e, scaled_max_m;
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- unsigned long scaled_rt_rp, new_rate;
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- int min_e = -1, min_e_m = -1, min_e_n = -1;
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+ int m, n, r, scaled_max_m;
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+ unsigned long scaled_rt_rp;
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+ unsigned long new_rate = 0;
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struct dpll_data *dd;
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if (!clk || !clk->dpll_data)
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@@ -311,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
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dd = clk->dpll_data;
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- pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
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- "%ld\n", clk->name, target_rate);
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+ pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
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+ clk->name, target_rate);
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scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
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scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
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@@ -347,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
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if (r == DPLL_MULT_UNDERFLOW)
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continue;
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- e = target_rate - new_rate;
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- pr_debug("clock: n = %d: m = %d: rate error is %d "
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- "(new_rate = %ld)\n", n, m, e, new_rate);
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-
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- if (min_e == -1 ||
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- min_e >= (int)(abs(e) - dd->rate_tolerance)) {
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- min_e = e;
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- min_e_m = m;
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- min_e_n = n;
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-
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- pr_debug("clock: found new least error %d\n", min_e);
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+ pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
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+ clk->name, m, n, new_rate);
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- /* We found good settings -- bail out now */
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- if (min_e <= dd->rate_tolerance)
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- break;
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+ if (target_rate == new_rate) {
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+ dd->last_rounded_m = m;
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+ dd->last_rounded_n = n;
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+ dd->last_rounded_rate = target_rate;
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+ break;
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}
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}
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- if (min_e < 0) {
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- pr_debug("clock: error: target rate or tolerance too low\n");
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+ if (target_rate != new_rate) {
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+ pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
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+ target_rate);
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return ~0;
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}
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- dd->last_rounded_m = min_e_m;
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- dd->last_rounded_n = min_e_n;
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- dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
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- min_e_m, min_e_n);
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-
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- pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
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- min_e, min_e_m, min_e_n);
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- pr_debug("clock: final rate: %ld (target rate: %ld)\n",
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- dd->last_rounded_rate, target_rate);
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-
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- return dd->last_rounded_rate;
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+ return target_rate;
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}
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Paul Walmsley