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+/*
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+ * Copyright (C) 2006 PA Semi, Inc
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+ *
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+ * Authors: Kip Walker, PA Semi
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+ * Olof Johansson, PA Semi
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+ *
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+ * Maintained by: Olof Johansson <olof@lixom.net>
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+ *
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+ * Based on arch/powerpc/platforms/maple/pci.c
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ */
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+
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+
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+#include <linux/kernel.h>
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+#include <linux/pci.h>
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+
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+#include <asm/pci-bridge.h>
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+#include <asm/machdep.h>
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+
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+#include <asm/ppc-pci.h>
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+
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+#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
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+
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+#define CONFIG_OFFSET_VALID(off) ((off) < 4096)
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+
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+static unsigned long pa_pxp_cfg_addr(struct pci_controller *hose,
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+ u8 bus, u8 devfn, int offset)
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+{
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+ return ((unsigned long)hose->cfg_data) + PA_PXP_CFA(bus, devfn, offset);
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+}
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+
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+static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
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+ int offset, int len, u32 *val)
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+{
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+ struct pci_controller *hose;
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+ unsigned long addr;
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+
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+ hose = pci_bus_to_host(bus);
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+ if (!hose)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ if (!CONFIG_OFFSET_VALID(offset))
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+ return PCIBIOS_BAD_REGISTER_NUMBER;
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+
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+ addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
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+
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+ /*
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+ * Note: the caller has already checked that offset is
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+ * suitably aligned and that len is 1, 2 or 4.
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+ */
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+ switch (len) {
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+ case 1:
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+ *val = in_8((u8 *)addr);
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+ break;
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+ case 2:
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+ *val = in_le16((u16 *)addr);
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+ break;
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+ default:
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+ *val = in_le32((u32 *)addr);
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+ break;
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+ }
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
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+ int offset, int len, u32 val)
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+{
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+ struct pci_controller *hose;
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+ unsigned long addr;
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+
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+ hose = pci_bus_to_host(bus);
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+ if (!hose)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ if (!CONFIG_OFFSET_VALID(offset))
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+ return PCIBIOS_BAD_REGISTER_NUMBER;
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+
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+ addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
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+
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+ /*
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+ * Note: the caller has already checked that offset is
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+ * suitably aligned and that len is 1, 2 or 4.
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+ */
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+ switch (len) {
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+ case 1:
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+ out_8((u8 *)addr, val);
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+ (void) in_8((u8 *)addr);
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+ break;
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+ case 2:
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+ out_le16((u16 *)addr, val);
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+ (void) in_le16((u16 *)addr);
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+ break;
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+ default:
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+ out_le32((u32 *)addr, val);
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+ (void) in_le32((u32 *)addr);
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+ break;
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+ }
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static struct pci_ops pa_pxp_ops = {
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+ pa_pxp_read_config,
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+ pa_pxp_write_config,
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+};
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+
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+static void __init setup_pa_pxp(struct pci_controller *hose)
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+{
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+ hose->ops = &pa_pxp_ops;
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+ hose->cfg_data = ioremap(0xe0000000, 0x10000000);
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+}
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+
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+static int __init add_bridge(struct device_node *dev)
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+{
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+ struct pci_controller *hose;
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+
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+ pr_debug("Adding PCI host bridge %s\n", dev->full_name);
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+
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+ hose = pcibios_alloc_controller(dev);
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+ if (!hose)
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+ return -ENOMEM;
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+
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+ hose->first_busno = 0;
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+ hose->last_busno = 0xff;
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+
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+ setup_pa_pxp(hose);
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+
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+ printk(KERN_INFO "Found PA-PXP PCI host bridge.\n");
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+
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+ /* Interpret the "ranges" property */
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+ /* This also maps the I/O region and sets isa_io/mem_base */
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+ pci_process_bridge_OF_ranges(hose, dev, 1);
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+ pci_setup_phb_io(hose, 1);
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+
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+ return 0;
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+}
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+
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+
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+void __init pas_pcibios_fixup(void)
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+{
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+ struct pci_dev *dev = NULL;
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+
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+ for_each_pci_dev(dev)
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+ pci_read_irq_line(dev);
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+}
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+
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+static void __init pas_fixup_phb_resources(void)
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+{
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+ struct pci_controller *hose, *tmp;
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+
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+ list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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+ unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
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+ hose->io_resource.start += offset;
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+ hose->io_resource.end += offset;
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+ printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
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+ hose->global_number,
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+ hose->io_resource.start, hose->io_resource.end);
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+ }
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+}
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+
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+
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+void __init pas_pci_init(void)
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+{
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+ struct device_node *np, *root;
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+
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+ root = of_find_node_by_path("/");
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+ if (!root) {
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+ printk(KERN_CRIT "pas_pci_init: can't find root "
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+ "of device tree\n");
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+ return;
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+ }
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+
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+ for (np = NULL; (np = of_get_next_child(root, np)) != NULL;)
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+ if (np->name && !strcmp(np->name, "pxp") && !add_bridge(np))
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+ of_node_get(np);
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+
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+ of_node_put(root);
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+
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+ pas_fixup_phb_resources();
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+
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+ /* Setup the linkage between OF nodes and PHBs */
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+ pci_devs_phb_init();
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+
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+ /* Use the common resource allocation mechanism */
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+ pci_probe_only = 1;
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+}
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