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@@ -0,0 +1,167 @@
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+/*
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+ * Copyright (C) ST-Ericsson SA 2010-2013
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+ * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
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+ * ST-Ericsson.
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+ * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
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+ * License terms: GNU General Public License (GPL) version 2
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/irqchip/arm-gic.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/platform_data/arm-ux500-pm.h>
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+
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+#include <mach/hardware.h>
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+
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+/* ARM WFI Standby signal register */
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+#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
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+#define PRCM_ARM_WFI_STANDBY_WFI0 0x08
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+#define PRCM_ARM_WFI_STANDBY_WFI1 0x10
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+#define PRCM_IOCR (prcmu_base + 0x310)
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+#define PRCM_IOCR_IOFORCE 0x1
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+
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+/* Dual A9 core interrupt management unit registers */
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+#define PRCM_A9_MASK_REQ (prcmu_base + 0x328)
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+#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
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+
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+#define PRCM_A9_MASK_ACK (prcmu_base + 0x32c)
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+#define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c)
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+#define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120)
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+#define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124)
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+#define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128)
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+#define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C)
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+#define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260)
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+#define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264)
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+#define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268)
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+#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C)
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+
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+static void __iomem *prcmu_base;
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+
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+/* This function decouple the gic from the prcmu */
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+int prcmu_gic_decouple(void)
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+{
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+ u32 val = readl(PRCM_A9_MASK_REQ);
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+
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+ /* Set bit 0 register value to 1 */
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+ writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
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+ PRCM_A9_MASK_REQ);
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+
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+ /* Make sure the register is updated */
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+ readl(PRCM_A9_MASK_REQ);
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+
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+ /* Wait a few cycles for the gic mask completion */
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+ udelay(1);
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+
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+ return 0;
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+}
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+
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+/* This function recouple the gic with the prcmu */
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+int prcmu_gic_recouple(void)
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+{
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+ u32 val = readl(PRCM_A9_MASK_REQ);
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+
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+ /* Set bit 0 register value to 0 */
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+ writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
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+
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+ return 0;
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+}
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+
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+#define PRCMU_GIC_NUMBER_REGS 5
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+
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+/*
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+ * This function checks if there are pending irq on the gic. It only
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+ * makes sense if the gic has been decoupled before with the
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+ * db8500_prcmu_gic_decouple function. Disabling an interrupt only
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+ * disables the forwarding of the interrupt to any CPU interface. It
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+ * does not prevent the interrupt from changing state, for example
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+ * becoming pending, or active and pending if it is already
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+ * active. Hence, we have to check the interrupt is pending *and* is
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+ * active.
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+ */
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+bool prcmu_gic_pending_irq(void)
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+{
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+ u32 pr; /* Pending register */
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+ u32 er; /* Enable register */
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+ void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
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+ int i;
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+
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+ /* 5 registers. STI & PPI not skipped */
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+ for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
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+
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+ pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
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+ er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
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+
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+ if (pr & er)
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+ return true; /* There is a pending interrupt */
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+ }
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+
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+ return false;
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+}
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+
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+/*
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+ * This function checks if there are pending interrupt on the
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+ * prcmu which has been delegated to monitor the irqs with the
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+ * db8500_prcmu_copy_gic_settings function.
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+ */
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+bool prcmu_pending_irq(void)
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+{
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+ u32 it, im;
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+ int i;
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+
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+ for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
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+ it = readl(PRCM_ARMITVAL31TO0 + i * 4);
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+ im = readl(PRCM_ARMITMSK31TO0 + i * 4);
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+ if (it & im)
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+ return true; /* There is a pending interrupt */
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+ }
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+
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+ return false;
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+}
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+
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+/*
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+ * This function checks if the specified cpu is in in WFI. It's usage
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+ * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
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+ * function. Of course passing smp_processor_id() to this function will
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+ * always return false...
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+ */
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+bool prcmu_is_cpu_in_wfi(int cpu)
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+{
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+ return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
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+ PRCM_ARM_WFI_STANDBY_WFI0;
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+}
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+
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+/*
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+ * This function copies the gic SPI settings to the prcmu in order to
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+ * monitor them and abort/finish the retention/off sequence or state.
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+ */
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+int prcmu_copy_gic_settings(void)
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+{
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+ u32 er; /* Enable register */
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+ void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
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+ int i;
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+
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+ /* We skip the STI and PPI */
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+ for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
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+ er = readl_relaxed(dist_base +
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+ GIC_DIST_ENABLE_SET + (i + 1) * 4);
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+ writel(er, PRCM_ARMITMSK31TO0 + i * 4);
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+ }
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+
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+ return 0;
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+}
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+
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+void __init ux500_pm_init(u32 phy_base, u32 size)
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+{
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+ prcmu_base = ioremap(phy_base, size);
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+ if (!prcmu_base) {
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+ pr_err("could not remap PRCMU for PM functions\n");
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+ return;
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+ }
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+ /*
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+ * On watchdog reboot the GIC is in some cases decoupled.
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+ * This will make sure that the GIC is correctly configured.
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+ */
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+ prcmu_gic_recouple();
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+}
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Linus Walleij