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@@ -490,46 +490,6 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
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}
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EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
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-/*
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- * Process a MIB interrupt. We may potentially be invoked because
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- * any of the MIB counters overflow/trigger so don't assume we're
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- * here because a PHY error counter triggered.
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- */
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-void ath9k_hw_proc_mib_event(struct ath_hw *ah)
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-{
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- u32 phyCnt1, phyCnt2;
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-
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- /* Reset these counters regardless */
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- REG_WRITE(ah, AR_FILT_OFDM, 0);
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- REG_WRITE(ah, AR_FILT_CCK, 0);
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- if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
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- REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
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-
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- /* Clear the mib counters and save them in the stats */
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- ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
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-
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- if (!DO_ANI(ah)) {
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- /*
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- * We must always clear the interrupt cause by
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- * resetting the phy error regs.
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- */
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- REG_WRITE(ah, AR_PHY_ERR_1, 0);
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- REG_WRITE(ah, AR_PHY_ERR_2, 0);
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- return;
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- }
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-
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- /* NB: these are not reset-on-read */
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- phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
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- phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
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- if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
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- ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
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-
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- /* NB: always restart to insure the h/w counters are reset */
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- ath9k_ani_restart(ah);
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- }
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-}
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-EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
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-
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void ath9k_hw_ani_setup(struct ath_hw *ah)
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{
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int i;
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