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@@ -117,8 +117,6 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
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static void ath9k_ani_restart(struct ath_hw *ah)
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{
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struct ar5416AniState *aniState;
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- struct ath_common *common = ath9k_hw_common(ah);
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- u32 ofdm_base = 0, cck_base = 0;
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if (!DO_ANI(ah))
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return;
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@@ -126,13 +124,10 @@ static void ath9k_ani_restart(struct ath_hw *ah)
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aniState = &ah->curchan->ani;
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aniState->listenTime = 0;
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- ath_dbg(common, ANI, "Writing ofdmbase=%u cckbase=%u\n",
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- ofdm_base, cck_base);
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-
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ENABLE_REGWRITE_BUFFER(ah);
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- REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
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- REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
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+ REG_WRITE(ah, AR_PHY_ERR_1, 0);
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+ REG_WRITE(ah, AR_PHY_ERR_2, 0);
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REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
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REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
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@@ -375,9 +370,6 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ar5416AniState *aniState = &ah->curchan->ani;
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- u32 ofdm_base = 0;
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- u32 cck_base = 0;
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- u32 ofdmPhyErrCnt, cckPhyErrCnt;
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u32 phyCnt1, phyCnt2;
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int32_t listenTime;
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@@ -397,15 +389,12 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
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phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
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phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
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- ofdmPhyErrCnt = phyCnt1 - ofdm_base;
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- ah->stats.ast_ani_ofdmerrs +=
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- ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
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- aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
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+ ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount;
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+ aniState->ofdmPhyErrCount = phyCnt1;
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+
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+ ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount;
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+ aniState->cckPhyErrCount = phyCnt2;
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- cckPhyErrCnt = phyCnt2 - cck_base;
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- ah->stats.ast_ani_cckerrs +=
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- cckPhyErrCnt - aniState->cckPhyErrCount;
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- aniState->cckPhyErrCount = cckPhyErrCnt;
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return true;
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}
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@@ -565,20 +554,19 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
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ath_dbg(common, ANI, "Initialize ANI\n");
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- ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
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- ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
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+ ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
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+ ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
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- ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
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- ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW;
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+ ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH;
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+ ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW;
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for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
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struct ath9k_channel *chan = &ah->channels[i];
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struct ar5416AniState *ani = &chan->ani;
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- ani->spurImmunityLevel =
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- ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
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+ ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
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- ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
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+ ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
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if (AR_SREV_9300_20_OR_LATER(ah))
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ani->mrcCCKOff =
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@@ -600,8 +588,8 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
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* since we expect some ongoing maintenance on the tables, let's sanity
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* check here default level should not modify INI setting.
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*/
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- ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
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- ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
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+ ah->aniperiod = ATH9K_ANI_PERIOD;
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+ ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL;
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if (ah->config.enable_ani)
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ah->proc_phyerr |= HAL_PROCESS_ANI;
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