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@@ -593,7 +593,7 @@ update_mboxes(struct intel_ring_buffer *ring,
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#define MBOX_UPDATE_DWORDS 4
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intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
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intel_ring_emit(ring, mmio_offset);
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- intel_ring_emit(ring, ring->outstanding_lazy_request);
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+ intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring, MI_NOOP);
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}
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@@ -629,7 +629,7 @@ gen6_add_request(struct intel_ring_buffer *ring)
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intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
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intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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- intel_ring_emit(ring, ring->outstanding_lazy_request);
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+ intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring, MI_USER_INTERRUPT);
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intel_ring_advance(ring);
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@@ -723,7 +723,7 @@ pc_render_add_request(struct intel_ring_buffer *ring)
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PIPE_CONTROL_WRITE_FLUSH |
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
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intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
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- intel_ring_emit(ring, ring->outstanding_lazy_request);
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+ intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring, 0);
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128; /* write to separate cachelines */
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@@ -742,7 +742,7 @@ pc_render_add_request(struct intel_ring_buffer *ring)
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
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PIPE_CONTROL_NOTIFY);
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intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
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- intel_ring_emit(ring, ring->outstanding_lazy_request);
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+ intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring, 0);
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intel_ring_advance(ring);
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@@ -963,7 +963,7 @@ i9xx_add_request(struct intel_ring_buffer *ring)
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intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
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intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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- intel_ring_emit(ring, ring->outstanding_lazy_request);
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+ intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring, MI_USER_INTERRUPT);
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intel_ring_advance(ring);
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@@ -1475,7 +1475,7 @@ int intel_ring_idle(struct intel_ring_buffer *ring)
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int ret;
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/* We need to add any requests required to flush the objects and ring */
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- if (ring->outstanding_lazy_request) {
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+ if (ring->outstanding_lazy_seqno) {
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ret = i915_add_request(ring, NULL);
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if (ret)
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return ret;
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@@ -1495,10 +1495,10 @@ int intel_ring_idle(struct intel_ring_buffer *ring)
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static int
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intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
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{
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- if (ring->outstanding_lazy_request)
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+ if (ring->outstanding_lazy_seqno)
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return 0;
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- return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
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+ return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
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}
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static int __intel_ring_begin(struct intel_ring_buffer *ring,
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@@ -1545,7 +1545,7 @@ void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
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{
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struct drm_i915_private *dev_priv = ring->dev->dev_private;
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- BUG_ON(ring->outstanding_lazy_request);
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+ BUG_ON(ring->outstanding_lazy_seqno);
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if (INTEL_INFO(ring->dev)->gen >= 6) {
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I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
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