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@@ -69,9 +69,6 @@ struct intel_limit {
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intel_p2_t p2;
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};
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-/* FDI */
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-#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
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-
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int
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intel_pch_rawclk(struct drm_device *dev)
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{
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@@ -4107,13 +4104,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
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struct drm_device *dev = crtc->base.dev;
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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- if (HAS_PCH_SPLIT(dev)) {
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- /* FDI link clock is fixed at 2.7G */
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- if (pipe_config->requested_mode.clock * 3
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- > IRONLAKE_FDI_FREQ * 4)
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- return -EINVAL;
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- }
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-
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/* Cantiga+ cannot handle modes with a hsync front porch of 0.
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* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
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*/
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