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+/*
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+ * Hardware modules present on the OMAP44xx chips
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+ *
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+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
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+ * Copyright (C) 2009-2010 Nokia Corporation
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+ *
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+ * Paul Walmsley
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+ * Benoit Cousson
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+ *
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+ * This file is automatically generated from the OMAP hardware databases.
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+ * We respectfully ask that any modifications to this file be coordinated
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+ * with the public linux-omap@vger.kernel.org mailing list and the
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+ * authors above to ensure that the autogeneration scripts are kept
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+ * up-to-date with the file contents.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/io.h>
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+
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+#include <plat/omap_hwmod.h>
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+#include <plat/cpu.h>
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+
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+#include "omap_hwmod_common_data.h"
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+
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+#include "cm.h"
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+#include "prm-regbits-44xx.h"
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+
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+/* Base offset for all OMAP4 interrupts external to MPUSS */
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+#define OMAP44XX_IRQ_GIC_START 32
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+
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+/* Base offset for all OMAP4 dma requests */
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+#define OMAP44XX_DMA_REQ_START 1
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+
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+/* Backward references (IPs with Bus Master capability) */
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+static struct omap_hwmod omap44xx_dmm_hwmod;
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+static struct omap_hwmod omap44xx_emif_fw_hwmod;
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+static struct omap_hwmod omap44xx_l3_instr_hwmod;
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+static struct omap_hwmod omap44xx_l3_main_1_hwmod;
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+static struct omap_hwmod omap44xx_l3_main_2_hwmod;
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+static struct omap_hwmod omap44xx_l3_main_3_hwmod;
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+static struct omap_hwmod omap44xx_l4_abe_hwmod;
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+static struct omap_hwmod omap44xx_l4_cfg_hwmod;
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+static struct omap_hwmod omap44xx_l4_per_hwmod;
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+static struct omap_hwmod omap44xx_l4_wkup_hwmod;
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+static struct omap_hwmod omap44xx_mpu_hwmod;
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+static struct omap_hwmod omap44xx_mpu_private_hwmod;
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+
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+/*
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+ * Interconnects omap_hwmod structures
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+ * hwmods that compose the global OMAP interconnect
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+ */
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+
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+/*
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+ * 'dmm' class
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+ * instance(s): dmm
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+ */
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+static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
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+ .name = "dmm",
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+};
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+
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+/* dmm interface data */
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+/* l3_main_1 -> dmm */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
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+ .master = &omap44xx_l3_main_1_hwmod,
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+ .slave = &omap44xx_dmm_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* mpu -> dmm */
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+static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
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+ .master = &omap44xx_mpu_hwmod,
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+ .slave = &omap44xx_dmm_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* dmm slave ports */
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+static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
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+ &omap44xx_l3_main_1__dmm,
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+ &omap44xx_mpu__dmm,
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+};
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+
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+static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
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+ { .irq = 113 + OMAP44XX_IRQ_GIC_START },
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+};
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+
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+static struct omap_hwmod omap44xx_dmm_hwmod = {
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+ .name = "dmm",
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+ .class = &omap44xx_dmm_hwmod_class,
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+ .slaves = omap44xx_dmm_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
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+ .mpu_irqs = omap44xx_dmm_irqs,
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+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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+};
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+
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+/*
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+ * 'emif_fw' class
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+ * instance(s): emif_fw
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+ */
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+static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
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+ .name = "emif_fw",
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+};
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+
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+/* emif_fw interface data */
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+/* dmm -> emif_fw */
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+static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
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+ .master = &omap44xx_dmm_hwmod,
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+ .slave = &omap44xx_emif_fw_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l4_cfg -> emif_fw */
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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+ .slave = &omap44xx_emif_fw_hwmod,
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+ .clk = "l4_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* emif_fw slave ports */
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+static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
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+ &omap44xx_dmm__emif_fw,
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+ &omap44xx_l4_cfg__emif_fw,
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+};
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+
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+static struct omap_hwmod omap44xx_emif_fw_hwmod = {
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+ .name = "emif_fw",
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+ .class = &omap44xx_emif_fw_hwmod_class,
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+ .slaves = omap44xx_emif_fw_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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+};
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+
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+/*
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+ * 'l3' class
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+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
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+ */
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+static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
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+ .name = "l3",
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+};
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+
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+/* l3_instr interface data */
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+/* l3_main_3 -> l3_instr */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
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+ .master = &omap44xx_l3_main_3_hwmod,
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+ .slave = &omap44xx_l3_instr_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l3_instr slave ports */
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+static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
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+ &omap44xx_l3_main_3__l3_instr,
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+};
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+
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+static struct omap_hwmod omap44xx_l3_instr_hwmod = {
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+ .name = "l3_instr",
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+ .class = &omap44xx_l3_hwmod_class,
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+ .slaves = omap44xx_l3_instr_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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+};
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+
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+/* l3_main_2 -> l3_main_1 */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
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+ .master = &omap44xx_l3_main_2_hwmod,
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+ .slave = &omap44xx_l3_main_1_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l4_cfg -> l3_main_1 */
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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+ .slave = &omap44xx_l3_main_1_hwmod,
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+ .clk = "l4_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* mpu -> l3_main_1 */
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+static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
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+ .master = &omap44xx_mpu_hwmod,
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+ .slave = &omap44xx_l3_main_1_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l3_main_1 slave ports */
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+static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
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+ &omap44xx_l3_main_2__l3_main_1,
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+ &omap44xx_l4_cfg__l3_main_1,
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+ &omap44xx_mpu__l3_main_1,
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+};
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+
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+static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
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+ .name = "l3_main_1",
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+ .class = &omap44xx_l3_hwmod_class,
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+ .slaves = omap44xx_l3_main_1_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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+};
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+
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+/* l3_main_2 interface data */
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+/* l3_main_1 -> l3_main_2 */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
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+ .master = &omap44xx_l3_main_1_hwmod,
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+ .slave = &omap44xx_l3_main_2_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l4_cfg -> l3_main_2 */
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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+ .slave = &omap44xx_l3_main_2_hwmod,
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+ .clk = "l4_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l3_main_2 slave ports */
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+static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
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+ &omap44xx_l3_main_1__l3_main_2,
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+ &omap44xx_l4_cfg__l3_main_2,
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+};
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+
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+static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
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+ .name = "l3_main_2",
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+ .class = &omap44xx_l3_hwmod_class,
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+ .slaves = omap44xx_l3_main_2_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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+};
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+
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+/* l3_main_3 interface data */
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+/* l3_main_1 -> l3_main_3 */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
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+ .master = &omap44xx_l3_main_1_hwmod,
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+ .slave = &omap44xx_l3_main_3_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l3_main_2 -> l3_main_3 */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
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+ .master = &omap44xx_l3_main_2_hwmod,
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+ .slave = &omap44xx_l3_main_3_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l4_cfg -> l3_main_3 */
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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+ .slave = &omap44xx_l3_main_3_hwmod,
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+ .clk = "l4_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l3_main_3 slave ports */
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+static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
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+ &omap44xx_l3_main_1__l3_main_3,
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+ &omap44xx_l3_main_2__l3_main_3,
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+ &omap44xx_l4_cfg__l3_main_3,
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+};
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+
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+static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
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+ .name = "l3_main_3",
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+ .class = &omap44xx_l3_hwmod_class,
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+ .slaves = omap44xx_l3_main_3_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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+};
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+
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+/*
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+ * 'l4' class
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+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
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+ */
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+static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
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+ .name = "l4",
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+};
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+
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+/* l4_abe interface data */
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+/* l3_main_1 -> l4_abe */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
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+ .master = &omap44xx_l3_main_1_hwmod,
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+ .slave = &omap44xx_l4_abe_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* mpu -> l4_abe */
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+static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
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+ .master = &omap44xx_mpu_hwmod,
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+ .slave = &omap44xx_l4_abe_hwmod,
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+ .clk = "ocp_abe_iclk",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l4_abe slave ports */
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+static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
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+ &omap44xx_l3_main_1__l4_abe,
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+ &omap44xx_mpu__l4_abe,
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+};
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+
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+static struct omap_hwmod omap44xx_l4_abe_hwmod = {
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+ .name = "l4_abe",
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+ .class = &omap44xx_l4_hwmod_class,
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+ .slaves = omap44xx_l4_abe_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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+};
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+
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+/* l4_cfg interface data */
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+/* l3_main_1 -> l4_cfg */
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
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+ .master = &omap44xx_l3_main_1_hwmod,
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+ .slave = &omap44xx_l4_cfg_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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+/* l4_cfg slave ports */
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+static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
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+ &omap44xx_l3_main_1__l4_cfg,
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+};
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+
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+static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
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+ .name = "l4_cfg",
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+ .class = &omap44xx_l4_hwmod_class,
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+ .slaves = omap44xx_l4_cfg_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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|
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+};
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|
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+
|
|
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+/* l4_per interface data */
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|
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+/* l3_main_2 -> l4_per */
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|
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+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
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+ .master = &omap44xx_l3_main_2_hwmod,
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+ .slave = &omap44xx_l4_per_hwmod,
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+ .clk = "l3_div_ck",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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|
|
+};
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|
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+
|
|
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+/* l4_per slave ports */
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|
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+static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
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+ &omap44xx_l3_main_2__l4_per,
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|
|
+};
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+
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+static struct omap_hwmod omap44xx_l4_per_hwmod = {
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+ .name = "l4_per",
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+ .class = &omap44xx_l4_hwmod_class,
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+ .slaves = omap44xx_l4_per_slaves,
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
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|
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+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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|
|
+};
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|
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+
|
|
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+/* l4_wkup interface data */
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|
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+/* l4_cfg -> l4_wkup */
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|
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+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
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+ .master = &omap44xx_l4_cfg_hwmod,
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|
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+ .slave = &omap44xx_l4_wkup_hwmod,
|
|
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+ .clk = "l4_div_ck",
|
|
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
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+
|
|
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+/* l4_wkup slave ports */
|
|
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+static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
|
|
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+ &omap44xx_l4_cfg__l4_wkup,
|
|
|
+};
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+
|
|
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+static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
|
|
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+ .name = "l4_wkup",
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|
|
+ .class = &omap44xx_l4_hwmod_class,
|
|
|
+ .slaves = omap44xx_l4_wkup_slaves,
|
|
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+ .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
|
|
|
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'mpu_bus' class
|
|
|
+ * instance(s): mpu_private
|
|
|
+ */
|
|
|
+static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
|
|
|
+ .name = "mpu_bus",
|
|
|
+};
|
|
|
+
|
|
|
+/* mpu_private interface data */
|
|
|
+/* mpu -> mpu_private */
|
|
|
+static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
|
|
|
+ .master = &omap44xx_mpu_hwmod,
|
|
|
+ .slave = &omap44xx_mpu_private_hwmod,
|
|
|
+ .clk = "l3_div_ck",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* mpu_private slave ports */
|
|
|
+static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
|
|
|
+ &omap44xx_mpu__mpu_private,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod omap44xx_mpu_private_hwmod = {
|
|
|
+ .name = "mpu_private",
|
|
|
+ .class = &omap44xx_mpu_bus_hwmod_class,
|
|
|
+ .slaves = omap44xx_mpu_private_slaves,
|
|
|
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
|
|
|
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'mpu' class
|
|
|
+ * mpu sub-system
|
|
|
+ */
|
|
|
+
|
|
|
+static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
|
|
|
+ .name = "mpu",
|
|
|
+};
|
|
|
+
|
|
|
+/* mpu */
|
|
|
+static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
|
|
|
+ { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
|
|
|
+ { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
|
|
|
+ { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
|
|
|
+};
|
|
|
+
|
|
|
+/* mpu master ports */
|
|
|
+static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
|
|
|
+ &omap44xx_mpu__l3_main_1,
|
|
|
+ &omap44xx_mpu__l4_abe,
|
|
|
+ &omap44xx_mpu__dmm,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod omap44xx_mpu_hwmod = {
|
|
|
+ .name = "mpu",
|
|
|
+ .class = &omap44xx_mpu_hwmod_class,
|
|
|
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
|
|
|
+ .mpu_irqs = omap44xx_mpu_irqs,
|
|
|
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
|
|
|
+ .main_clk = "dpll_mpu_m2_ck",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
|
|
|
+ },
|
|
|
+ },
|
|
|
+ .masters = omap44xx_mpu_masters,
|
|
|
+ .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
|
|
|
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
|
|
+};
|
|
|
+
|
|
|
+static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
|
|
|
+ /* dmm class */
|
|
|
+ &omap44xx_dmm_hwmod,
|
|
|
+ /* emif_fw class */
|
|
|
+ &omap44xx_emif_fw_hwmod,
|
|
|
+ /* l3 class */
|
|
|
+ &omap44xx_l3_instr_hwmod,
|
|
|
+ &omap44xx_l3_main_1_hwmod,
|
|
|
+ &omap44xx_l3_main_2_hwmod,
|
|
|
+ &omap44xx_l3_main_3_hwmod,
|
|
|
+ /* l4 class */
|
|
|
+ &omap44xx_l4_abe_hwmod,
|
|
|
+ &omap44xx_l4_cfg_hwmod,
|
|
|
+ &omap44xx_l4_per_hwmod,
|
|
|
+ &omap44xx_l4_wkup_hwmod,
|
|
|
+ /* mpu_bus class */
|
|
|
+ &omap44xx_mpu_private_hwmod,
|
|
|
+
|
|
|
+ /* mpu class */
|
|
|
+ &omap44xx_mpu_hwmod,
|
|
|
+ NULL,
|
|
|
+};
|
|
|
+
|
|
|
+int __init omap44xx_hwmod_init(void)
|
|
|
+{
|
|
|
+ return omap_hwmod_init(omap44xx_hwmods);
|
|
|
+}
|
|
|
+
|
Tony Lindgren