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@@ -75,6 +75,7 @@ struct spi_imx_devtype_data {
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int (*config)(struct spi_imx_data *, struct spi_imx_config *);
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int (*config)(struct spi_imx_data *, struct spi_imx_config *);
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void (*trigger)(struct spi_imx_data *);
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void (*trigger)(struct spi_imx_data *);
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int (*rx_available)(struct spi_imx_data *);
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int (*rx_available)(struct spi_imx_data *);
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+ void (*reset)(struct spi_imx_data *);
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};
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};
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struct spi_imx_data {
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struct spi_imx_data {
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@@ -213,7 +214,7 @@ static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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}
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-static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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+static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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struct spi_imx_config *config)
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{
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{
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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@@ -221,12 +222,7 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
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reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
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MX31_CSPICTRL_DR_SHIFT;
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MX31_CSPICTRL_DR_SHIFT;
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- if (cpu_is_mx31())
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- reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
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- else if (cpu_is_mx25() || cpu_is_mx35()) {
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- reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
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- reg |= MX31_CSPICTRL_SSCTL;
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- }
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+ reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
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if (config->mode & SPI_CPHA)
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if (config->mode & SPI_CPHA)
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reg |= MX31_CSPICTRL_PHA;
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reg |= MX31_CSPICTRL_PHA;
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@@ -235,10 +231,7 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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if (config->mode & SPI_CS_HIGH)
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if (config->mode & SPI_CS_HIGH)
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reg |= MX31_CSPICTRL_SSPOL;
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reg |= MX31_CSPICTRL_SSPOL;
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if (config->cs < 0) {
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if (config->cs < 0) {
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- if (cpu_is_mx31())
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- reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
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- else if (cpu_is_mx25() || cpu_is_mx35())
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- reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
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+ reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
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}
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}
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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@@ -246,11 +239,43 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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return 0;
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return 0;
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}
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}
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+static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
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+ struct spi_imx_config *config)
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+{
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+ unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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+
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+ reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
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+ MX31_CSPICTRL_DR_SHIFT;
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+
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+ reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
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+ reg |= MX31_CSPICTRL_SSCTL;
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+
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+ if (config->mode & SPI_CPHA)
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+ reg |= MX31_CSPICTRL_PHA;
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+ if (config->mode & SPI_CPOL)
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+ reg |= MX31_CSPICTRL_POL;
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+ if (config->mode & SPI_CS_HIGH)
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+ reg |= MX31_CSPICTRL_SSPOL;
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+ if (config->cs < 0)
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+ reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
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+
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+ writel(reg, spi_imx->base + MXC_CSPICTRL);
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+
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+ return 0;
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+}
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+
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static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
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static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
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{
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{
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return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
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return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
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}
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}
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+static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
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+{
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+ /* drain receive buffer */
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+ while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
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+ readl(spi_imx->base + MXC_CSPIRXDATA);
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+}
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+
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#define MX27_INTREG_RR (1 << 4)
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#define MX27_INTREG_RR (1 << 4)
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#define MX27_INTREG_TEEN (1 << 9)
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#define MX27_INTREG_TEEN (1 << 9)
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#define MX27_INTREG_RREN (1 << 13)
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#define MX27_INTREG_RREN (1 << 13)
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@@ -313,6 +338,11 @@ static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
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return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
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return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
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}
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}
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+static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx)
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+{
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+ writel(1, spi_imx->base + MXC_RESET);
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+}
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+
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#define MX1_INTREG_RR (1 << 3)
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#define MX1_INTREG_RR (1 << 3)
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#define MX1_INTREG_TEEN (1 << 8)
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#define MX1_INTREG_TEEN (1 << 8)
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#define MX1_INTREG_RREN (1 << 11)
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#define MX1_INTREG_RREN (1 << 11)
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@@ -369,6 +399,11 @@ static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
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return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
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return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
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}
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}
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+static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
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+{
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+ writel(1, spi_imx->base + MXC_RESET);
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+}
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+
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/*
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/*
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* These version numbers are taken from the Freescale driver. Unfortunately it
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* These version numbers are taken from the Freescale driver. Unfortunately it
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* doesn't support i.MX1, so this entry doesn't match the scheme. :-(
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* doesn't support i.MX1, so this entry doesn't match the scheme. :-(
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@@ -380,6 +415,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
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.config = mx1_config,
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.config = mx1_config,
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.trigger = mx1_trigger,
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.trigger = mx1_trigger,
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.rx_available = mx1_rx_available,
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.rx_available = mx1_rx_available,
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+ .reset = mx1_reset,
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},
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},
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#endif
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#endif
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#ifdef CONFIG_SPI_IMX_VER_0_0
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#ifdef CONFIG_SPI_IMX_VER_0_0
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@@ -388,22 +424,25 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
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.config = mx27_config,
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.config = mx27_config,
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.trigger = mx27_trigger,
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.trigger = mx27_trigger,
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.rx_available = mx27_rx_available,
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.rx_available = mx27_rx_available,
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+ .reset = spi_imx0_0_reset,
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},
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},
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#endif
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#endif
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#ifdef CONFIG_SPI_IMX_VER_0_4
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#ifdef CONFIG_SPI_IMX_VER_0_4
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[SPI_IMX_VER_0_4] = {
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[SPI_IMX_VER_0_4] = {
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.intctrl = mx31_intctrl,
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.intctrl = mx31_intctrl,
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- .config = mx31_config,
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+ .config = spi_imx0_4_config,
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.trigger = mx31_trigger,
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.trigger = mx31_trigger,
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.rx_available = mx31_rx_available,
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.rx_available = mx31_rx_available,
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+ .reset = spi_imx0_4_reset,
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},
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},
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#endif
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#endif
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#ifdef CONFIG_SPI_IMX_VER_0_7
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#ifdef CONFIG_SPI_IMX_VER_0_7
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[SPI_IMX_VER_0_7] = {
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[SPI_IMX_VER_0_7] = {
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.intctrl = mx31_intctrl,
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.intctrl = mx31_intctrl,
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- .config = mx31_config,
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+ .config = spi_imx0_7_config,
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.trigger = mx31_trigger,
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.trigger = mx31_trigger,
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.rx_available = mx31_rx_available,
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.rx_available = mx31_rx_available,
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+ .reset = spi_imx0_4_reset,
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},
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},
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#endif
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#endif
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};
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};
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@@ -683,13 +722,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
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clk_enable(spi_imx->clk);
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clk_enable(spi_imx->clk);
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spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
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spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
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- if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
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- writel(1, spi_imx->base + MXC_RESET);
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-
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- /* drain receive buffer */
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- if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
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- while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
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- readl(spi_imx->base + MXC_CSPIRXDATA);
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+ spi_imx->devtype_data.reset(spi_imx);
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spi_imx->devtype_data.intctrl(spi_imx, 0);
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spi_imx->devtype_data.intctrl(spi_imx, 0);
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