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@@ -511,6 +511,10 @@ static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
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.enable_tx_low_pwr_on_siso_rdl = 0x00,
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.rx_profile = 0x00,
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.pwr_limit_reference_11_abg = 0xc8,
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+ .psat = 0,
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+ .low_power_val = 0x00,
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+ .med_power_val = 0x0a,
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+ .high_power_val = 0x1e,
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},
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};
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@@ -713,6 +717,7 @@ static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
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struct wl18xx_priv *priv = wl->priv;
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struct wl18xx_conf_phy *phy = &priv->conf.phy;
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struct wl18xx_mac_and_phy_params params;
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+ size_t len;
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memset(¶ms, 0, sizeof(params));
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@@ -752,9 +757,21 @@ static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
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params.board_type = priv->board_type;
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+ /* for PG2 only */
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+ params.psat = phy->psat;
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+ params.low_power_val = phy->low_power_val;
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+ params.med_power_val = phy->med_power_val;
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+ params.high_power_val = phy->high_power_val;
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+
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+ /* the parameters struct is smaller for PG1 */
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+ if (wl->chip.id == CHIP_ID_185x_PG10)
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+ len = offsetof(struct wl18xx_mac_and_phy_params, psat) + 1;
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+ else
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+ len = sizeof(params);
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+
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wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
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wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)¶ms,
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- sizeof(params), false);
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+ len, false);
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}
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static void wl18xx_enable_interrupts(struct wl1271 *wl)
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