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@@ -115,6 +115,29 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
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return 0;
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}
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+static int ar8031_phy_fixup(struct phy_device *dev)
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+{
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+ u16 val;
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+
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+ /* To enable AR8031 output a 125MHz clk from CLK_25M */
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+ phy_write(dev, 0xd, 0x7);
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+ phy_write(dev, 0xe, 0x8016);
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+ phy_write(dev, 0xd, 0x4007);
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+
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+ val = phy_read(dev, 0xe);
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+ val &= 0xffe3;
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+ val |= 0x18;
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+ phy_write(dev, 0xe, val);
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+
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+ /* introduce tx clock delay */
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+ phy_write(dev, 0x1d, 0x5);
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+ val = phy_read(dev, 0x1e);
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+ val |= 0x0100;
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+ phy_write(dev, 0x1e, val);
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+
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+ return 0;
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+}
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+
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static void __init imx6q_sabrelite_cko1_setup(void)
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{
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struct clk *cko1_sel, *ahb, *cko1;
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@@ -139,11 +162,15 @@ put_clk:
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clk_put(cko1);
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}
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+#define PHY_ID_AR8031 0x004dd074
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+
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static void __init imx6q_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB)) {
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phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
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ksz9021rn_phy_fixup);
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+ phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
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+ ar8031_phy_fixup);
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}
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}
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