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@@ -315,10 +315,6 @@ static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
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jiffies_to_msecs(trans_pcie->wd_timeout));
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IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
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txq->q.read_ptr, txq->q.write_ptr);
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- IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
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- iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq->q.id))
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- & (TFD_QUEUE_SIZE_MAX - 1),
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- iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq->q.id)));
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iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
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@@ -328,6 +324,28 @@ static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
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IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
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iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
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+ for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
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+ u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
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+ u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
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+ bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
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+ u32 tbl_dw =
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+ iwl_read_targ_mem(trans,
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+ trans_pcie->scd_base_addr +
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+ SCD_TRANS_TBL_OFFSET_QUEUE(i));
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+
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+ if (i & 0x1)
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+ tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
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+ else
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+ tbl_dw = tbl_dw & 0x0000FFFF;
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+
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+ IWL_ERR(trans,
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+ "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
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+ i, active ? "" : "in", fifo, tbl_dw,
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+ iwl_read_prph(trans,
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+ SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
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+ iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
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+ }
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+
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iwl_op_mode_nic_error(trans->op_mode);
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}
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