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@@ -42,17 +42,6 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
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#define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
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PPC_FEATURE_HAS_MMU)
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-/* We only set the altivec features if the kernel was compiled with altivec
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- * support
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- */
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-#ifdef CONFIG_ALTIVEC
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-#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
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-#define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
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-#else
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-#define CPU_FTR_ALTIVEC_COMP 0
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-#define PPC_FEATURE_ALTIVEC_COMP 0
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-#endif
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-
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/* We only set the spe features if the kernel was compiled with
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* spe support
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*/
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@@ -62,34 +51,13 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
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#define PPC_FEATURE_SPE_COMP 0
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#endif
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-/* We need to mark all pages as being coherent if we're SMP or we
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- * have a 74[45]x and an MPC107 host bridge.
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- */
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-#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
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-#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
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-#else
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-#define CPU_FTR_COMMON 0
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-#endif
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-
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-/* The powersave features NAP & DOZE seems to confuse BDI when
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- debugging. So if a BDI is used, disable theses
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- */
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-#ifndef CONFIG_BDI_SWITCH
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-#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
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-#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
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-#else
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-#define CPU_FTR_MAYBE_CAN_DOZE 0
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-#define CPU_FTR_MAYBE_CAN_NAP 0
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-#endif
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-
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struct cpu_spec cpu_specs[] = {
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#if CLASSIC_PPC
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{ /* 601 */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00010000,
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.cpu_name = "601",
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- .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
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- CPU_FTR_HPTE_TABLE,
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+ .cpu_features = CPU_FTRS_PPC601,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
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PPC_FEATURE_UNIFIED_CACHE,
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.icache_bsize = 32,
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@@ -100,9 +68,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00030000,
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.cpu_name = "603",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_603,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -112,9 +78,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00060000,
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.cpu_name = "603e",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_603,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -124,9 +88,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00070000,
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.cpu_name = "603ev",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_603,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -136,9 +98,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00040000,
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.cpu_name = "604",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
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+ .cpu_features = CPU_FTRS_604,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -149,9 +109,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xfffff000,
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.pvr_value = 0x00090000,
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.cpu_name = "604e",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
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+ .cpu_features = CPU_FTRS_604,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -162,9 +120,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00090000,
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.cpu_name = "604r",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
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+ .cpu_features = CPU_FTRS_604,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -175,9 +131,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x000a0000,
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.cpu_name = "604ev",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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- CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
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+ .cpu_features = CPU_FTRS_604,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -188,10 +142,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffffffff,
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.pvr_value = 0x00084202,
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.cpu_name = "740/750",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
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- CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_740_NOTAU,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -202,10 +153,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xfffffff0,
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.pvr_value = 0x00080100,
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.cpu_name = "750CX",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_750,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -216,10 +164,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xfffffff0,
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.pvr_value = 0x00082200,
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.cpu_name = "750CX",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_750,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -230,10 +175,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xfffffff0,
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.pvr_value = 0x00082210,
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.cpu_name = "750CXe",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_750,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -244,10 +186,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffffffff,
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.pvr_value = 0x00083214,
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.cpu_name = "750CXe",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_750,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -258,10 +197,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xfffff000,
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.pvr_value = 0x00083000,
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.cpu_name = "745/755",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_750,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -272,11 +208,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffffff00,
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.pvr_value = 0x70000100,
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.cpu_name = "750FX",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
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- CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
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+ .cpu_features = CPU_FTRS_750FX1,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -287,11 +219,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffffffff,
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.pvr_value = 0x70000200,
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.cpu_name = "750FX",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
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- CPU_FTR_NO_DPM,
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+ .cpu_features = CPU_FTRS_750FX2,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -302,11 +230,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x70000000,
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.cpu_name = "750FX",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
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- CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
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+ .cpu_features = CPU_FTRS_750FX,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -317,11 +241,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x70020000,
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.cpu_name = "750GX",
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- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
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- CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
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- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
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- CPU_FTR_HAS_HIGH_BATS,
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+ .cpu_features = CPU_FTRS_750GX,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -332,10 +252,7 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00080000,
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.cpu_name = "740/750",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
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+ .cpu_features = CPU_FTRS_740,
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.cpu_user_features = COMMON_PPC,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -346,11 +263,8 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffffffff,
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.pvr_value = 0x000c1101,
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.cpu_name = "7400 (1.1)",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
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- CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
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- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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+ .cpu_features = CPU_FTRS_7400_NOTAU,
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+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.num_pmcs = 4,
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@@ -360,12 +274,8 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x000c0000,
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.cpu_name = "7400",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
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- CPU_FTR_MAYBE_CAN_NAP,
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- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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+ .cpu_features = CPU_FTRS_7400,
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+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.num_pmcs = 4,
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@@ -375,12 +285,8 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x800c0000,
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.cpu_name = "7410",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
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- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
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- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
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- CPU_FTR_MAYBE_CAN_NAP,
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- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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+ .cpu_features = CPU_FTRS_7400,
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+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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.num_pmcs = 4,
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@@ -390,12 +296,8 @@ struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0xffffffff,
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.pvr_value = 0x80000200,
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.cpu_name = "7450",
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- .cpu_features = CPU_FTR_COMMON |
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- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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- CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_NEED_COHERENT,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7450_20,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -405,14 +307,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffffffff,
|
|
|
.pvr_value = 0x80000201,
|
|
|
.cpu_name = "7450",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
|
|
|
- CPU_FTR_NEED_COHERENT,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7450_21,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -422,13 +318,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x80000000,
|
|
|
.cpu_name = "7450",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7450_23,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -438,12 +329,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffffff00,
|
|
|
.pvr_value = 0x80010100,
|
|
|
.cpu_name = "7455",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7455_1,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -453,14 +340,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffffffff,
|
|
|
.pvr_value = 0x80010200,
|
|
|
.cpu_name = "7455",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
|
|
|
- CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7455_20,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -470,14 +351,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x80010000,
|
|
|
.cpu_name = "7455",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
|
|
|
- CPU_FTR_NEED_COHERENT,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7455,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -487,14 +362,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffffffff,
|
|
|
.pvr_value = 0x80020100,
|
|
|
.cpu_name = "7447/7457",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
|
|
|
- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7447_10,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -504,14 +373,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffffffff,
|
|
|
.pvr_value = 0x80020101,
|
|
|
.cpu_name = "7447/7457",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
|
|
|
- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7447_10,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -521,14 +384,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x80020000,
|
|
|
.cpu_name = "7447/7457",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
|
|
|
- CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
|
|
|
- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
|
|
|
- CPU_FTR_NEED_COHERENT,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7447,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -538,13 +395,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x80030000,
|
|
|
.cpu_name = "7447A",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
|
|
|
- CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
|
|
|
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7447A,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -554,13 +406,8 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x80040000,
|
|
|
.cpu_name = "7448",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
|
|
|
- CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
|
|
|
- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_7447A,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
|
.num_pmcs = 6,
|
|
@@ -570,9 +417,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0x7fff0000,
|
|
|
.pvr_value = 0x00810000,
|
|
|
.cpu_name = "82xx",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_82XX,
|
|
|
.cpu_user_features = COMMON_PPC,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -582,9 +427,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0x7fff0000,
|
|
|
.pvr_value = 0x00820000,
|
|
|
.cpu_name = "G2_LE",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
|
|
|
+ .cpu_features = CPU_FTRS_G2_LE,
|
|
|
.cpu_user_features = COMMON_PPC,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -594,9 +437,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0x7fff0000,
|
|
|
.pvr_value = 0x00830000,
|
|
|
.cpu_name = "e300",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
|
|
|
+ .cpu_features = CPU_FTRS_E300,
|
|
|
.cpu_user_features = COMMON_PPC,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -606,9 +447,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0x00000000,
|
|
|
.pvr_value = 0x00000000,
|
|
|
.cpu_name = "(generic PPC)",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_HPTE_TABLE,
|
|
|
+ .cpu_features = CPU_FTRS_CLASSIC32,
|
|
|
.cpu_user_features = COMMON_PPC,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -620,9 +459,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x00400000,
|
|
|
.cpu_name = "Power3 (630)",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_HPTE_TABLE,
|
|
|
+ .cpu_features = CPU_FTRS_POWER3_32,
|
|
|
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
|
|
|
.icache_bsize = 128,
|
|
|
.dcache_bsize = 128,
|
|
@@ -633,9 +470,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x00410000,
|
|
|
.cpu_name = "Power3 (630+)",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_HPTE_TABLE,
|
|
|
+ .cpu_features = CPU_FTRS_POWER3_32,
|
|
|
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
|
|
|
.icache_bsize = 128,
|
|
|
.dcache_bsize = 128,
|
|
@@ -646,9 +481,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x00360000,
|
|
|
.cpu_name = "I-star",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_HPTE_TABLE,
|
|
|
+ .cpu_features = CPU_FTRS_POWER3_32,
|
|
|
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
|
|
|
.icache_bsize = 128,
|
|
|
.dcache_bsize = 128,
|
|
@@ -659,9 +492,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x00370000,
|
|
|
.cpu_name = "S-star",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_HPTE_TABLE,
|
|
|
+ .cpu_features = CPU_FTRS_POWER3_32,
|
|
|
.cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
|
|
|
.icache_bsize = 128,
|
|
|
.dcache_bsize = 128,
|
|
@@ -670,44 +501,12 @@ struct cpu_spec cpu_specs[] = {
|
|
|
},
|
|
|
#endif /* CONFIG_PPC64BRIDGE */
|
|
|
#ifdef CONFIG_POWER4
|
|
|
- { /* Power4 */
|
|
|
- .pvr_mask = 0xffff0000,
|
|
|
- .pvr_value = 0x00350000,
|
|
|
- .cpu_name = "Power4",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_HPTE_TABLE,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
|
|
|
- .icache_bsize = 128,
|
|
|
- .dcache_bsize = 128,
|
|
|
- .num_pmcs = 8,
|
|
|
- .cpu_setup = __setup_cpu_power4
|
|
|
- },
|
|
|
- { /* PPC970 */
|
|
|
- .pvr_mask = 0xffff0000,
|
|
|
- .pvr_value = 0x00390000,
|
|
|
- .cpu_name = "PPC970",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_HPTE_TABLE |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
|
|
|
- PPC_FEATURE_ALTIVEC_COMP,
|
|
|
- .icache_bsize = 128,
|
|
|
- .dcache_bsize = 128,
|
|
|
- .num_pmcs = 8,
|
|
|
- .cpu_setup = __setup_cpu_ppc970
|
|
|
- },
|
|
|
{ /* PPC970FX */
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x003c0000,
|
|
|
.cpu_name = "PPC970FX",
|
|
|
- .cpu_features = CPU_FTR_COMMON |
|
|
|
- CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
|
|
|
- CPU_FTR_HPTE_TABLE |
|
|
|
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
|
|
|
- .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
|
|
|
- PPC_FEATURE_ALTIVEC_COMP,
|
|
|
+ .cpu_features = CPU_FTRS_970_32,
|
|
|
+ .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
|
|
|
.icache_bsize = 128,
|
|
|
.dcache_bsize = 128,
|
|
|
.num_pmcs = 8,
|
|
@@ -721,8 +520,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.cpu_name = "8xx",
|
|
|
/* CPU_FTR_MAYBE_CAN_DOZE is possible,
|
|
|
* if the 8xx code is there.... */
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_8XX,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 16,
|
|
|
.dcache_bsize = 16,
|
|
@@ -733,8 +531,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffffff00,
|
|
|
.pvr_value = 0x00200200,
|
|
|
.cpu_name = "403GC",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 16,
|
|
|
.dcache_bsize = 16,
|
|
@@ -743,8 +540,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffffff00,
|
|
|
.pvr_value = 0x00201400,
|
|
|
.cpu_name = "403GCX",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 16,
|
|
|
.dcache_bsize = 16,
|
|
@@ -753,8 +549,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x00200000,
|
|
|
.cpu_name = "403G ??",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 16,
|
|
|
.dcache_bsize = 16,
|
|
@@ -763,8 +558,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x40110000,
|
|
|
.cpu_name = "405GP",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -774,8 +568,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x40130000,
|
|
|
.cpu_name = "STB03xxx",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -785,8 +578,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x41810000,
|
|
|
.cpu_name = "STB04xxx",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -796,8 +588,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x41610000,
|
|
|
.cpu_name = "NP405L",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -807,8 +598,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x40B10000,
|
|
|
.cpu_name = "NP4GS3",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -818,8 +608,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x41410000,
|
|
|
.cpu_name = "NP405H",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -829,8 +618,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x50910000,
|
|
|
.cpu_name = "405GPr",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -840,8 +628,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x51510000,
|
|
|
.cpu_name = "STBx25xx",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -851,8 +638,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x41F10000,
|
|
|
.cpu_name = "405LP",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -861,8 +647,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x20010000,
|
|
|
.cpu_name = "Virtex-II Pro",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -872,8 +657,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xffff0000,
|
|
|
.pvr_value = 0x51210000,
|
|
|
.cpu_name = "405EP",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_40X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
|
|
|
.icache_bsize = 32,
|
|
@@ -886,8 +670,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xf0000fff,
|
|
|
.pvr_value = 0x40000850,
|
|
|
.cpu_name = "440EP Rev. A",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -896,8 +679,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xf0000fff,
|
|
|
.pvr_value = 0x400008d3,
|
|
|
.cpu_name = "440EP Rev. B",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -906,8 +688,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xf0000fff,
|
|
|
.pvr_value = 0x40000440,
|
|
|
.cpu_name = "440GP Rev. B",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -916,8 +697,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xf0000fff,
|
|
|
.pvr_value = 0x40000481,
|
|
|
.cpu_name = "440GP Rev. C",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -926,8 +706,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xf0000fff,
|
|
|
.pvr_value = 0x50000850,
|
|
|
.cpu_name = "440GX Rev. A",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -936,8 +715,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xf0000fff,
|
|
|
.pvr_value = 0x50000851,
|
|
|
.cpu_name = "440GX Rev. B",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -946,8 +724,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xf0000fff,
|
|
|
.pvr_value = 0x50000892,
|
|
|
.cpu_name = "440GX Rev. C",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -956,8 +733,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xf0000fff,
|
|
|
.pvr_value = 0x50000894,
|
|
|
.cpu_name = "440GX Rev. F",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -966,8 +742,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0xff000fff,
|
|
|
.pvr_value = 0x53000891,
|
|
|
.cpu_name = "440SP Rev. A",
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_44X,
|
|
|
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|
|
@@ -979,7 +754,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_value = 0x81000000,
|
|
|
.cpu_name = "e200z5",
|
|
|
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
|
|
|
- .cpu_features = CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_E200,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
|
|
|
PPC_FEATURE_UNIFIED_CACHE,
|
|
@@ -990,7 +765,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_value = 0x81100000,
|
|
|
.cpu_name = "e200z6",
|
|
|
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
|
|
|
- .cpu_features = CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_E200,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
|
|
|
PPC_FEATURE_HAS_EFP_SINGLE |
|
|
@@ -1002,8 +777,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_value = 0x80200000,
|
|
|
.cpu_name = "e500",
|
|
|
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB,
|
|
|
+ .cpu_features = CPU_FTRS_E500,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
|
|
|
PPC_FEATURE_HAS_EFP_SINGLE,
|
|
@@ -1016,8 +790,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_value = 0x80210000,
|
|
|
.cpu_name = "e500v2",
|
|
|
/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
|
|
|
- .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
|
|
|
- CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
|
|
|
+ .cpu_features = CPU_FTRS_E500_2,
|
|
|
.cpu_user_features = PPC_FEATURE_32 |
|
|
|
PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
|
|
|
PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
|
|
@@ -1031,7 +804,7 @@ struct cpu_spec cpu_specs[] = {
|
|
|
.pvr_mask = 0x00000000,
|
|
|
.pvr_value = 0x00000000,
|
|
|
.cpu_name = "(generic PPC)",
|
|
|
- .cpu_features = CPU_FTR_COMMON,
|
|
|
+ .cpu_features = CPU_FTRS_GENERIC_32,
|
|
|
.cpu_user_features = PPC_FEATURE_32,
|
|
|
.icache_bsize = 32,
|
|
|
.dcache_bsize = 32,
|